Educational
Sessions
Sunday,
September 10
For
complete write ups on the Educational Sessions, click on the Educational
Sessions button, under Conference Events
Educational Session 1 -
Integrated
Phase-Locked Systems – Optimization and Trends
E1-1,
Fractional-N PLLs for Frequency
Synthesis,
Ian Galton,
E1-2,
Mixed-Signal Approaches for PLL Design and Implementation
Michael Perrott, Mass. Inst. of
Technology
E1-3,
Noise Properties of VCOs in PLLs
Ali Hajimiri, the California Institute of Electrical
Engineering
E1-4,
Device and Circuit Modeling for Phase-Locked
Systems
Behzad Razavi,
Educational Session 2 -
Advanced
RF Design Techniques
E2-1,
Circuit Design for Impulse and MB-OFDM UWB
Domine Leenaerts,
Philips
E2-2,
E2-3,
Power Amplifier Design Techniques
Mihai Banu, MHI
Consulting
E2-4Technology-Aware
ESD-Reliable RF CMOS Circuit Design
Dimitri Linten, IMEC/Vrije
Universiteit Brussel, Belgium
Educational Session 3 -
High
Performance and Low Power Digital Circuit
Design
E3-1,
Low-Power and Low-Voltage Circuit Technologies for Energy-Efficient DSP
Design
E3-2,
Clockless Circuits as a Silent Digital Companion for
Analog and RF
Ad Peeters, Handshake Solutions
E3-3,
Ultra Low Power/Voltage Design
Jan M. Rabaey,
E3-4,
Variability, A Barrier to Further CMOS
Scaling?
Marcel
J. M. Pelgrom, Philips
Technical
Sessions
Monday,
September 11 – Wednesday, September 13
Session
1 – Keynote Session
Monday
Morning, September 11
Oak
Ballroom
8:00
am
Welcome and Opening
Remarks
Awards
Presentation
Keynote Speaker
Introduction – Henry Chang, Conference Chair
8:20
am Keynote Presentation
Dr. Sanjay K.
Jha, Executive
Vice President of QUALCOMM Incorporated and President of QUALCOMM CDMA
Technologies
The
Evolution of Semiconductor Needs in Handsets
Looking
to the future of mobile devices, there will be key applications that
exponentially drive the growth of this platform even beyond the dramatic growth
expected over the next few years.
There are many opportunities in the wireless space, and as a leader of
this industry, QUALCOMM CDMA Technologies (QCT) has a unique vision into what
the future holds. Technology coming
to market today is often called "3G," so what will 4G look like? What types of groundbreaking services
will be possible, and how will the semiconductors powering these next-generation
devices need to evolve in order to power the new functionality in a
still-attractive form-factor? Dr.
Sanjay K. Jha, president of QCT, will explore the
changing landscape of this industry and explain the technology innovations
necessary to bring these visions of the future to
reality.
Session
2 – Advances in Analog and Digital Programmable
Devices
Monday
Morning, September 11
Oak
Ballroom
Chair: Steve Wilton,
Co-Chair: Arif Rahman,
Xilinx
Programmable devices provide a low-cost, low-risk path
to complex analog, digital, and mixed-signal implementations. This session highlights circuit and
architectural techniques that make these devices
possible.
2.1 -
10:05
Low-Voltage
Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal
FPGAs, L. Kalyani-Garimella, A.Garimella, J. Ramirez-Angulo,
R. Carvajal, A. Lopez-Martin, New
Mexico State University, Las Cruces, NM
A novel, highly versatile general
purpose analog/digital/neural configurable logic block (LVUC) for utilization in
the next generation of Mixed Signal FPGAs is introduced. It is very compact and
has low power, low voltage requirements and operates with rail-to-rail analog
and digital signals. It can be easily configured as: digital, analog, analog to
digital, digital to analog and neural programmable block. To the author’s
knowledge this is the first mixed signal FPGA logic block
reported.
2.2 -
10:30
A
Large-Scale Reconfigurable Analog Signal Processor (RASP)
IC, C. Twigg, P. Hasler, Georgia Institute of Technology,
Atlanta, GA
The Reconfigurable Analog Signal
Processor (RASP), one of the first Large-Scale Field-Programmable Analog Arrays
(FPAAs), is composed of 56 Computational Analog Blocks (CABs). Each CAB contains
various levels of analog computational granularity utilizing over 50,000
programmable analog elements. Bias currents are programmable to within 0.2% from
100 pA to greater than 3 uA. Internal bandwidths are greater than 50 MHz, and
the kT/C noise can be adjusted using the drawn capacitances and routing network
parasitics. A range of compiled circuits and resulting signal processing systems
are presented.
2.3 -
10:55
Determination
of Power Gating Granularity for FPGA Fabric, A. Rahman, S. Das, T. Tuan, S. Trimberger, Xilinx
Research Laboratories, San Jose, CA
In this study, we present a design
methodology to determine the granularity of power gating for Field Programmable
Gate Arrays (FPGAs). Fine-grain power gating is more effective than coarse-grain
power gating to reduce the active leakage power of unused logic and
interconnection resources. However, the area overhead in fine-grain power gating
is higher than that of coarse-grain power gating. Based on the placement and
routing of benchmark designs in Spartan-3TM-like FPGA, guidelines for
determining the granularity of power gating are provided. It is found that
programmable resources with low utilization can be power gated more coarsely
than the resources with high utilization.
2.4 -
11:20
Reconfigurable
Asynchronous Logic (INVITED PAPER), R. Manohar,
Challenges in mapping asynchronous
logic to a flexible substrate include developing a balance between circuit-level
flexibility, mapping complexity, and logic overhead. We have developed a
reconfigurable dataflow architecture that addresses these challenges, and have
also created the necessary synthesis flow required to map designs to the
architecture. The architecture exploits some of the unique features of
asynchronous logic, and attains a performance that significantly exceeds
previous asynchronous FPGAs.
Session
3 – RF Techniques
Monday
Morning, September 11
Fir
Ballroom
Chair: John
Rogers,
Co-Chair:
This
session explores advances circuits techniques that address timely issues such as
working at extremely high frequencies and at very low voltage. New topologies for LANs, oscillators,
and dividers will be presented.
3.1 -
10:05
A
50-GHz Phase-Locked Loop in 130-nm CMOS, C. Cao, Y. Ding and K. O, University of Florida,
Gainesville, FL
A 50-GHz PLL utilizing an
LC-oscillator based injection locked divider is fabricated in a 130-nm logic
CMOS process. The PLL can be locked from 45.9 to 50.5GHz. The circuit including
buffers consumes 57mW from 1.5/0.8V supplies. The phase noise at 50kHz, 1MHz and
10MHz offset from the carrier is -63.5, -72, and -99dBc/Hz, respectively. The
PLL also outputs -22-dBm second order harmonic frequencies between 91.8 and
101GHz.
3.2 -
10:30
Common
Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS
Front-End, A. Liscidini, C. Ghezzi,
A new topology of transformer based
low noise amplifier is presented. The structure realizes a low noise input match
and a current gain greater than one by a current to current positive feedback
closed around a common gate stage. The amplifier is inserted in a high linearity
current mode RF front-end receiver working between 4.15-4.4GHz with a NF of
4.2dB, a gain of 24.2dB and an IIP3 of -2dBm.
3.3 -
10:55
Passive
& Active Control of Regenerative Standing & Soliton Waves (Invited
Paper), W.
Andress, D. Ricketts, X. Li and D. Ham,
This paper reviews two recently
developed wave-control technologies [1,2] for wave-based oscillators. In [1],
the fields of a standing wave hosted by a transmission line are sculpted to
better suit the unique standing wave properties; this passive wave control is
achieved by tapering the line and reduces phase noise. In [2] we constructed an
oscillator that self-generates a periodic train of electrical solitons. An
active amplifier controls the unruly soliton dynamics to guarantee oscillation
stability.
3.4 -
11:45
A
0.9-V Double-Balanced Quadrature-Input Quadrature-Output Frequency
Divider, H. Zheng and H. Luong, The Hong Kong University of
Science and Technology, Hong Kong
A double-balanced quadrature-input
quadrature-output (QIQO) divider is proposed. By making use of the quadrature
phase outputs from a quadrature VCO (QVCO), the QIQO divider provides a
mechanism to achieve an output IQ phase sequence that is inherently tracked with
the input IQ phase sequence. Moreover, compared with conventional dividers, the
QIQO divider not only provides smaller and better-matched input loading to the
QVCO but also improved quadrature phase accuracy. Fabricated in a 0.18-µm CMOS
process and operated at 0.9 V, the QIQO divider measures an image rejection of
-62 dBc while consuming 7.2 mW.
Session
4 – Delta-Sigma Converters
Monday
Morning, September 11
Pine
Ballroom
Chair:
Kathleen Philips, Philips Research
The
papers in this session discuss innovative circuits and architectures advancing
the performance of Delta-Sigma A/D converters.
4.1 -
10:05
Incremental
Delta-Sigma Structures for DC Measurement: an Overview (INVITED
PAPER), J. Markus, P. Deval*, V. Quiquempoix*, J. Silva** and
G. Temes**,
In this paper the operation and
design of incremental delta-sigma converters is reviewed. Two different analyses
of the first-order converter are presented, and two extensions to higher-order
modulators are proposed. Since line-frequency noise suppression is often
important in measurement applications, modulators followed by sinc filters are
also analyzed. Equations are derived to estimate the required number of cycles.
Finally, the implementation of a 22-bit third-order incremental converter is
discussed.
4.2 -
10:55
A
14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path
Cascode Amplifiers, Z. Cao,
T. Song and S. Yan, The
Switched-capacitor biased
pseudo-differential split-path cascode amplifiers are proposed to achieve high
power efficiency and small die area for a 14-bit 2.5MS/s sigma-delta modulator.
Sufficient power supply and common mode rejection is achived through the
innovative biasing circuit and signal/reference sampling network. A prototype
chip is fabricated in 0.25um CMOS with 0.27mm^2 core area. Experimental results
show that 84dB DR is achieved with the 1.25MHz signal bandwidth and 14mW power
dissipation when clocked at 120MHz.
4.3 -
11:20
A
100-MS/s 4-MHz Bandwidth 77.3-dB SNDR DS ADC with a Triple Sampling
Technique, Y. Kanazawa, Y. Fujimoto, P. Lo Ré and M. Miyamoto,
Sharp Corporation,
A new DS ADC architecture using a
triple sampling technique and a two-step summation scheme is presented. A
4th-order switched-capacitor DS ADC with a 4-bit quantizer is designed for a
low-power direct-conversion digital TV receiver SoC. It achieves a 77.3-dB SNDR
over a 4-MHz bandwidth with a 100-MHz clock frequency. The chip, fabricated in a
0.18-um CMOS process, occupies 1.57 mm2 and draws 15.3 mA from a 1.8-V supply.
It achieves a 0.58-pJ/conversion FOM.
4.4 -
11:45
A
2.7mW 2MHz Continuous-Time Sigma-Delta Modulator with a Hybrid Active-Passive
Loop Filter, T. Song, Z. Cao and S. Yan, The University of Texas at
Austin, Austin, TX
We present a 5th-order
continuous-time sigma-delta modulator with three amplifiers. Part of the loop
filter is implemented as active integrators, and part as passive ones. A
switched-capacitor feedback DAC is employed for high clock jitter immunity.
Another current steering DAC stabilizes the loop. A prototype sigma-delta
modulator with 2MHz signal bandwidth is designed in 0.25um CMOS, experimentally
achieving 68dB DR over 2MHz bandwidth clocked at 150MHz, while consuming 1.8mA
from 1.5V supply.
Session
5 – Measurement Techniques for High Speed
Signals
Monday
Morning, September 11
Cedar
Ballroom
Chair:
Jeanne Trinko-Mechler, IBM
Co-Chair:
On-chip
signal digitization and capture at 70-GHz is presented in the first paper. Next is offered a jitter and link
characterization tutorial which addresses standards such as PCI Express, Fibre Channel, and Giga Bit Ethernet. A novel bus probing technique based on
electromagnetic couplers is presented in the third paper. The session closes with an innovative
circuit design which allows a two order improvement in characterization accuracy
of the frequency response of on-chip continuous-time
filters.
5.1 -
10:05
A
70-GHz Effective Sampling Rate On-Chip Oscilloscope with Time-Domain
Digitization, M. Safi-Harb and G. Roberts,
An on-chip digitizer for the
transient measurement of digital signal integrity is proposed. Undersampling,
combined with single-path time-domain processing is used to perform the embedded
measurement in a time-efficient manner. On-chip interconnect crosstalk
generation with variable strength is included on chip for characterization, and
successfully measured using a prototype chip, implemented in a 0.18 µm CMOS
process. The proposed system is easily calibratable, with an estimated static
power dissipation of ~ 3.5 mW. The total active area taken up by the associated
test and calibration vehicles is 0.45 mm2.
5.2 -
10:30
Jitter
And Signaling Test For High-Speed Links (INVITED PAPER), M. Li, Wavecrest Corporation,
We reviewed the roles that jitter and
signaling plays in a high speed communication link. We then discuss the testing
and verification methods for the link components of transmitter, receiver,
medium, and reference clock. The latest statistical plus system transfer
function based jitter and signaling test methods are introduced. Finally, we
reviewed the jitter and signaling in leading Gbps communication standards and
associated test requirements and methods.
5.3 -
11:20
A
8 Gb/s Electromagnetic Coupler Transceiver, T. Hinck, J. Critchlow, T. Wig, J. Benham and L. Tate,
Intel Corporation, Hudson, MA
Abstract - An analog transceiver is
detailed, which recovers electromagnetically coupled signals from a link that is
under test. The link data must be DC-balanced, i.e. 8b10b encoded, due to the
coupler’s AC nature. The coupler’s signal is recovered by an integrating circuit
architecture with equalization. Test results show that the EM transceiver works
down to input amplitudes of 42mVdiffpp (BER: 10-12) at 8 Gb/s. The receiver was
designed in a 90nm CMOS process at 1.2 volts.
5.4 -
11:45
A
Technique for Accurate Frequency Response Measurement of Integrated
Continuous-Time Filters, S. Pavan and T. Laxminidhi, Indian Institute of
Technology,
We present a technique to accurately
characterize the frequency response of high frequency on-chip continuous-time
filters. When compared to conventional methods of measurement, the proposed
technique shows two orders of magnitude improvement in accuracy. Experimental
results are shown for a 75\,MHz fifth order Chebyshev Gm-C ladder filter
designed in a 0.35\,$\mu\rm{m}$ CMOS process and packaged in a 40 pin
dual-in-line package. The measured response is accurate upto
400\,MHz.
Session
6 – Power Optimized RF and Wireline SoC’s
Monday
Afternoon, September 11
Oak
Ballroom
Chair:
Co-Chair:
The first four papers present software-assisted GSM
radio RF processing, 802.11 WLAN integration, multiprocessing and integrated
power management for wireless products. The next
four papers present SoCs with 6.375 Gb/s SerDes I/Os, 22.5 Gb/s
cross-current and a 10 Gb/s framer. A human-body network
processor with less than 30uW power, and a 15 dB SNR substrate noise reduction
for wireline
networks.
6.1 -
1:35
Software
Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm
CMOS, R. Staszewski, T. Jung, B. Staszewski, K. Muhammad, D.
Leipold, T. Murphy, S. Sabin, J. Wallberg, S. Larson, M. Entezari, J. Fresquez,
S. Dondershine and S. Syed, Texas Instruments, Dallas,
TX
This paper describes a new software
and application programming interface view of an RF transceiver as implemented
in the first single-chip GSM radio in 90~nm CMOS. It demonstrates benefits of
using programmable digital control logic in deep-submicron CMOS RF system. It
also describes a micro-processor architecture design in Digital RF Processor
(DRP) and how it controls compensation for process, temperature and voltage
variations of the analog and RF circuits to meet the required RF
performance.
6.2 -
2:00
A
Highly Integrated Power Management IC for Advanced
Design of power management is
becoming a more complex problem for advanced mobile devices. In this paper, a
highly integrated power management IC (PMIC) is presented which enables mobile
devices that are more cost-effective, thinner and more compact with better power
efficiency. The overall
architecture and system level design considerations are described. The design
details of a key building block – low-dropout linear regulator (LDO) – are also
discussed, including a novel frequency compensation method.
6.3 -
2:25
A
Dual-Band Triple-Mode SoC for 802.11a/b/g Embedded WLAN in 90nm
CMOS, A. Shirvani, D. Cheung, R. Tsang, S. Jamal, T. Cho, X.
Jin and Y. Song, Marvell Semiconductor, Santa Clara,
CA
An 802.11a/b/g-compliant SoC
integrates a WLAN system, comprising a dual-band RF transceiver and PHY, MAC and
ARM processor units, in 90nm CMOS. Challenges of SoC integration in 90nm CMOS
and the mitigation techniques are discussed, along with circuit design
techniques to optimize RF performance in 90nm. For 54Mb/s signals, the receiver
sensitivity is -75dBm/-72dBm at 2.4GHz/5GHz, where the transmitter achieves an
EVM of -35dB/-32dB at 0dBm output power.
6.4 -
2:50
Design
and implementation of a reconfigurable heterogeneous multiprocessor
SoC, M. Bocchi, M. De Dominicis, C. Mucci, A. Deledda, F.
Campi*, A. Lodi, M. Toma* and R. Guerrieri, University of Bologna, Bologna,
Italy, *STMicroelectronics, Brianza, Italy
This paper introduces a novel
heterogeneous shared memory multiprocessor architecture based on a
reconfigurable processor and a standard RISC processor. The work demonstrates
that coupling a reconfigurable core to a RISC core leads to a computational
density increase by a factor of up to 1.7x on signal processing applications
with a 37% energy saving. The multi-core SoC architecture was implemented in
0.13 µm technology, achieving a 166MHz clock frequency with an average 340mW
power consumption.
6.5 -
3:35
Embedded
Mixed-Signal IP Development Methodology in 90nm CMOS SerDes
FPGAs, R. Patel and W. Bereza*, Altera Corporation,
A 275mW at 6.375Gbps High Speed
Serial Interface developed in TSMC’s 90nm TGO CMOS process and the customized
methodology applied to develop and integrate high-speed mixed-signal IPs into
FPGA platforms will be presented. The risk reduction approach used ensured
reliable product, with timely availability. The transceiver IP supports multiple
protocols such as PCIe, XAUI, CEI, SDI, etc,. The transceiver achieves better
than 10^-12 BER at 6.375Gbps.
6.6 -
4:00
Integrated
155M-10Gbps Framer with 22.5Gbps Low/High Order Cross Connect
SoC, K. Venkataraman, V. Suresh, S. Iyengar, M. Ott, S.
Kalari, J. Zhi, E. Ruetz, M. Gray,
B. Reynov and A. Iqbal, Crimson Microsystems, Inc.
The advent of broadband services
requires Multi Service Provisioning Platforms (MSPP) to achieve >10Gbps
capacity with 1-4 rack unit footprint, power <200W and cost <$10K. Highly
integrated SoC using 0.13 micron CMOS 19.3x19.3mm die packaged in a 1517 FCBGA
affords a unique MSPP solution consisting of 155M-10Gbps SONET/SDH framing,
low/high order path processing, grooming, cross-connection up to 22.5Gbps and an
embedded processor. A rigorous
methodology enabled a production-worthy SoC comprising 9Mgates/14Mbit
memory.
6.7 -
4:25
Comparison
and Impact of Substrate Noise Generated by Clocked and Clockless Digital
Circuitry, J. Le, C. Hanken, M. Held, M. Hagedorn, K. Mayaram and
T. Fiez,
A pseudo-random number generator
implemented in asynchronous logic generates one-fifth the RMS substrate noise as
the equivalent design in synchronous logic. An asynchronous 8051 processor
generates one-third the RMS substrate noise as the equivalent synchronous
design. The SNR of a second order delta-sigma modulator (DSM) is not affected by
substrate noise due to an asynchronous processor while it experiences 15 dB
degradation when the synchronous processor is clocked near integer multiples of
the sampling frequency.
6.8 -
4:50
A
Multi-Nodes Human Body Communication Sensor Network Control
Processor,
This paper presents a low-power body
sensor network (BSN) control processor for human body communication (HBC) with
the performance of 254 nodes management. The proposed ‘instantaneous program
execution with external program counter’ scheme provides up to 10-MIPS
performance only when it is needed, and the ‘TCAM-based period scheduler’
manages 254 HBC nodes with 21.6-uW power consumption. They are verified by the
implementation of the BSN controller and shows 254 nodes management with
4.2-MIPS performance.
Session
7 –
Monday
Afternoon, September 11
Fir
Ballroom
Chair:
Co-Chair:
The
session starts with an invited paper on low-power design challenges, followed by
advances in wireless transmitter building blocks, including direct modulators, a
wide-band VCO, and high-efficiency PA techniques.
7.1 -
1:35
Challenges
in Designing Low-Power Wireless Systems-on-a-Chip (INVITED
PAPER), D. Su, Atheros Communications, Inc.,
This paper describes the challenges
in designing low-power CMOS systems-on-a-chip for wireless communications. RF
transceiver building blocks for signal amplification, frequency translation, and
frequency selectivity are examined with special emphasis on low noise amplifier,
power amplifier, mixer, and frequency synthesizer. System-on-a-chip integration
issues to relevant to a low-power CMOS design are also
discussed.
7.2 -
2:25
A
2.4GHz direct modulated 0.18um CMOS IEEE 802.15.4 compliant Transmitter for
ZigBee, S. Beyer, R. Jaehne, W. Kluge and D. Eggert, Atmel,
Drresden, Germany
This paper presents an improved
fractional-N based transmitter architecture, fully compliant with ZigBee IEEE
802.15.4 standard. Operating in the 2.4GHz ISM frequency range, the fractional-N
PLL based synthesizer architecture achieves an integrated phase noise of
2.6degrms. The transmitter error-vector magnitude (EVM) for MSK modulated
signals is 5.3% with an output level of approximately +4dBm. This transmitter is
incorporated in a single-chip RF transceiver providing a complete
antenna-to-micro controller radio interface.
7.3 -
2:50
A
Wideband Delta Sigma Digital-RF Modulator With Self-Tuned RF Bandpass
Reconstruction Filter, A. Jerng and C. Sodini, Massachusetts Institute of
Technology, Cambridge, MA
A low power, wideband transmitter
architecture utilizing Delta-Sigma direct digital modulation of an RF carrier is
presented. Spurious signals associated with direct digital-RF conversion are
eliminated through integration of a self-tuned passive LC bandpass filter. The
digital-RF modulator is intended for OFDM systems and can provide data rates
greater than 1 Gb/s using a bandwidth of 200 MHz centered at 5.25 GHz. Measured
results show that the largest modulator spur is -44 dBc.
7.4 -
3:35
Quad
Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm
CMOS, S.
Akhtar, M. Ipek, J. Lin, R. Staszewski and P. Litmanen, Texas
Instruments, Inc.,
We present the first published
implementation and measurements of a fully integrated phase path for a 3G polar
transmitter in deep sub micron CMOS. It includes a single quad-band digitally
controlled oscillator (DCO) providing modulation capability to handle the wide
bandwidth of the WCDMA phase (frequency) data and a switched inverter divider.
The complete chip, with integrated LDOs, consumes 20mA from a 1.4V supply while
providing a PN of -157dBc/Hz at a 40MHz offset for a 2GHz
output
7.5 -
4:00
Low-power
CMOS IEEE 802.11a/g Signal Separator for Outphasing
Transmitter, L. Panseri, L. Romanň, S. Levantino, C. Samori and A.
Lacaita, Politecnico di Milano, Milan, Italy
This paper presents an all-analog
signal component separator for a Wireless-LAN outphasing transmitter. The
proposed circuit derives the two constant-envelope components of the OFDM signal
in analog domain at baseband, allowing for power consumption considerably lower
than digital implementations. This separator integrated in 0.25-um CMOS passes
all the tests of the 54-Mb/s IEEE 802.11a/g standard, with no calibration
between the two paths. The power consumption is 45mW from a 2.5-V voltage
supply.
7.6 -
4:25
A
Novel DAC Based Switching Power Amplifier for Polar
Transmitter, A. Shameli, A. Safarian, A. Rofougaran*, M.
Rofougaran* and F. De Flaviis, University of California, Irvine, CA, *Broadcom
Corporation, Irvine, CA
A novel switching power amplifier
based on the concept of D/A converter is presented for polar transmitter. This
amplifier generates a current proportional to the amplitude modulation signal
and the power control bits. The current is then up-converted to the frequency of
interest using switching transistors. The measurement results show maximum
output power of 27.8dBm with power efficiency of 34%. Moreover, the amplifier
exhibits amplitude modulation bandwidth of 4.2MHz and 62dB power control dynamic
range.
7.7 -
4:50
A
1.2V, 2.4GHz Fully Integrated Linear CMOS Power Amplifier with Efficiency
Enhancement, G. Liu, T-J. Liu and A. Niknejad,
A 2.4GHz power amplifier is
implemented with standard thin-oxide transistors in a 1.2V, 0.13 micron CMOS
process. The output matching network is fully integrated on chip. The PA
transmits up to 24dBm linear power with 25% drain efficiency at -1dB compression
point. A technique for enhancing average efficiency is proposed and
demonstrated. This technique does not degrade instantaneous efficiency at peak
power and maintains constant power gain with power back-off.
Session
8 – D/A Converters
Monday
Afternoon, September 11
Pine
Ballroom
Chiar:
Co-Chair: L. Richard Carley,
This
session covers DACs from an oversampled one with >100dB DR to a 90nm CMOS one clocked
at 1GHz, and addresses proximity effects in sub-100nm
CMOS.
8.1 -
1:35
A
4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization
Structure, Y-H.
Lee, M-Y. Choi, S-B. You, W-S. Yeum, H-J. Park and J-W. Kim, Samsung
Electronics, Co., Ltd.,
A 2.7V 4mW per-channel 20-bit 48kS/s
sigma-delta stereo audio DAC, integrated in a 0.13um CMOS technology, achieves a
dynamic range (DR) of 101dB and occupies an active die area of 0.82mm2. The
transformed quantization technique is proposed to decrease tonal behavior
generated in low order sigma-delta modulator and the circuit is implemented to
operate with optimal current consumption. The measured SNR and peak SNDR are
102dB and 95dB, respectively.
8.2 -
2:00
Design
of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS
resistors,
We present an implementation of a
4-bit binary-weighted-resistor DAC to be used in quantizers. It is built by
using tunable floating-gate CMOS resistors, which exploit the capacitive
coupling and voltage storage capabilities of floating-gate transistors and
employ scaled-gate linearization technique to suppress the MOSFET
nonlinearities. The resistance of these resistors drifts 1.6*10^-3 over the
period of 10 years at 25C. By using these resistors, 15-bit accurate DAC is
implemented in 0.5um CMOS process.
8.3 -
2:25
Low
Power Approaches To High Speed CMOS Current Steering DACs (INVITED
PAPER), D. Mercer, Analog Devices Inc.,
This paper discusses a number of
circuit approaches which address lowering the power consumed by a modern current
steering DAC while maintaining both DC and AC performance levels. An example
design provides 14 bit resolution and 250 MSPS conversion rate in a 1P4M 0.18um
CMOS process, with optional 3.3 volt compatible devices. A power
dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was
achieved for 1.8V operation and as low as 0.28 mW/MSPS at 3.3V. SFDR of 70 dB is
achieved at a 50 MHz output frequency.
8.4 -
2:50
An
Area Optimized 2.5-V 10-b 200-MS/s 200-uA CMOS DAC, B. Nejati and L. Larson*, Sequoia Communications,
A 10b 200MHz digital-to-analog
converter is optimized for low power and low area with ±25%, 0.1% incremental
gain control. The converter uses a combined thermometer coded current-steering
DAC and an R-2R load to achieve a compact layout and sub-µA LSB current. It
provides more than 61dB spurious-free dynamic range over 50MHz bandwidth within
–20°C to +95°C temperature range from a dual 2.5/1.8V supply. The differential
and integral non-linearity of the converter are within ±0.1LSB. The 0.55mm x
0.47mm converter is implemented in a 0.35/0.18µm CMOS technology and the DAC
core dissipates 200µA static current from a 2.5V analog
supply.
8.5 -
3:35
A
10-bit 1GSample/s DAC in 90nm CMOS for Embedded
Applications, J. Cao, H. Lin, Y. Xiang, C. Kao and K. Dyer*, KT
Micro, Inc., Rancho Santa Margarita, CA, *Keyeye Communications, Sacremento,
CA
A 90nm CMOS 10-bit 1GS/s
current-steering D/A converter is presented. Fabricated in TSMC 1P9M 90nm CMOS
process, it dissipates a core power of 49mW, the lowest reported at this
performance level. It occupies 0.36 mm^2. Using only five power/ground pins, it
is designed and optimized for next generation high-speed digital communication
SoCs. 72dB SFDR and 9.2 ENOB with a full-scale 41.3MHz input at 800MS/s are
measured. At 1.05GS/s, 68dB SFDR with 54.3MHz input is
achieved.
8.6 -
4:00
Implications
of Proximity Effects for Analog Design (INVITED PAPER), P. Drennan, M. Kniffin and D. Locascio, Freescale
Semiconductor,
This paper addresses two significant
proximity effects, well proximity and STI stress, as they related to analog
circuit design. Device performance is impacted by layout features located near,
but not part of the device. This adds new complexities to analog design. In
either case, bias points can shift by 20-30%, potentially causing catastrophic
failures in circuits. We show, for the first time, that a MOSFET placed close to
a well-edge creates a graded channel.
Session
9 – Advanced Analog Verification Technique
Monday
Afternoon, September 11
Cedar
Ballroom
Chair:
Larry Nagel, Omega Enterprises
Co-Chair:
This
session addresses new modeling and circuit verification techniques that are
required for the design of increasingly complex, sophisticated, and mainly
analog portions of VLSI integrated circuits.
9.1 -
1:35
Verification
of Complex Analog Integrated Circuits (INVITED PAPER), K. Kundert and H. Chang, Designer's Guide Consulting,
Inc.,
Functional complexity in analog,
mixed-signal, and RF (A/RF) designs is increasing dramatically. A/RF designs
implement many modes of operation for different standards, power saving modes,
and calibration. Increasingly, catastrophic failures in chips are due to
functional bugs, and not due to missed performance specifications. Functionally
verifying A/ RF designs is a daunting task requiring a rigorous and systematic
verification methodology. This paper describes a verification methodology to
address these challenges.
9.2 -
2:25
On-the-Fly
Fidelity Assessment for Trajectory-Based Circuit
Macromodels, S. Tiwary and R. Rutenbar, Carnegie Mellon University,
Pittsburgh, PA
Trajectory methods offer an
attractive methodology for automated extraction of macromodels from a set of
training simulations. A pervasive concern with models based on regression is the
lack of certainty about where they fit correctly. We show how the unique
structure of a scalable trajectory model allows it to monitor the "fidelity" of
the fit automatically, and flag where additional model training is warranted.
Experimental results demonstrate this self-monitoring ability in practical
circuit examples.
9.3 -
2:50
Predictive
Modeling of the NBTI Effect for Reliable Design, S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao and S.
Vrudhula, Arizona State University, Tempe, AZ
This paper presents a predictive
model for the Negative Bias
Temperature Instability (NBTI) of PMOS under both short term and long term operation. Based on the
reaction-diffusion mechanism, this
model captures the dependence of NBTI on
the oxide thickness, the diffusing species and other key transistor and design
parameters. In addition, we derive
an expression for the threshold voltage change under multiple cycle dynamic
operation. Model accuracy and efficiency were verified with 90-nm experimental
and simulation
data.
9.4 -
3:35
Modeling,
Design, and Verification for the Analog Front-end of a MEMS-based Parallel
Scanning-probe Storage Device, C. Hagleitner, A. Bonaccio*, H. Rothuizen, D.
Wiesmann, J. Lienemann, J. Korvink**, G. Cherubini and E. Eleftheriou, IBM
Zurich Research Lab, Ruschlikon, Switzerland, *IBM Systems & Technology
Group, Burlington, VT, **University of Freiburg, Freiburg,
Ger
We present the modeling, design and
experimental verification of an integrated analog front-end for the read-channel
of a parallel scanning-probe storage device (“millipede”). A detailed model of
the microfabricated read/write head based on a combination of a
thermal/electrical lumped-element model and an automatically generated
behavioral model (from a full finite-element model) of the
electrostatic/mechanical part was developed. The model is coded in Verilog-A and
was used to co-develop the read-out circuitry and the read/write
cantilever.
9.5 -
4:00
Modeling
Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta
Modulator, K. Abdelfattah and B. Razavi,
A system-level methodology for the
inclusion of op amp nonlinearity in discrete-time integrators and sigma-delta
modulators is proposed that consists of a hyperbolic tangent model for the
input/output characteristic of op amps and a recursive solution of nonlinear
integrators. Simulations at different levels of abstraction indicate that the
methodology incurs an error of no more than 1.1 dB in the magnitude of harmonics
while providing a 50x advantage in the simulation speed with respect to
transistor-level implementations.
9.6 -
4:25
Rapid
Simulation of Current Steering Digital-to-Analog Converters using
Verilog-A, M. Shanmugasundaram and S. Pavan, Indian Institute of
technology,
We present a technique to drastically
reduce the simulation time of current-steering DACs, while maintaining the
accuracy of a full transistor level simulation. Time varying current controlled
current sources (implemented in Verilog-A) are used to simplify the thermometer
portion of the DAC, thereby reducing device count and simulation time. A
comparison of the results of our technique with a full transistor level 10-bit
DAC operating at 500\,Msps shows that a speed-up of 40X is achievable, with no
loss of accuracy.
Session
10 – Advanced Memories
Tuesday
Morning, September 12
Oak
Ballroom
Chair: Phil
Diodato, Agere Systems
Co-Chair:
Next
generation DRAM technology and FIN-FET SRAMs are
presented. Exhaustive SER analysis
and low cost test methods are described.
10.1 -
8:05
Device
Technology for Embedded DRAM Utilizing Stacked MIM(Metal-Insulator-Metal)
Capacitor (INVITED PAPER), Y.
Yamagata, H. Shirai, H. Sugimura, S. Arai, T. Wake, K. Inoue, T. Sakoh,
M. Sakao, and T. Tanigawa, NEC
Electronics Corporation, Kanagawa, Japan
This paper presents embedded DRAM
device technology utilizing stacked MIM(Metal-Insulator-Metal) capacitor.
Targeted for high random-access and low-power data-streaming applications, "Full
Metal DRAM”technology has been devised and implemented. It features reduced
parasitic resistance of DRAM cell and full CMOS compatibility.In 90nm
generation, ZrO2 capacitor is newly introduced. In 55nm generation, high-k gate
dielectric(HfSiON)implemented in CMOS platform will be exploited for embedded
DRAM performance improvement.
10.2 -
8:55
A
Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on
SOI, K.
Arimoto, F. Morishita, I. Hayashi, T. Tanizaki, T. Ipposhi, and K.
Dosaka, Renesas Technology Corporation,
We propose a capacitor-less SOI
memory with scalable function named SETRAM (Scalable Enhanced Twin-transistor
RAM). The scalable functions are, for example, 263MHz high speed random cycle
memory to replace the high density on chip SRAM, 79mW/4Mb lower active power
dissipation for mobile application, 453MHz data transfer of page/burst mode for
cache memory and graphics memory applications and lower stand-by current mode of
5 sec data retention time. These are also supported as the programmable
functions.
10.3 -
9:20
Optimization
Of Surface Orientation For High-Performance, Low-Power And Robust FinFET
SRAM, S. Gangwal, S. Mukhopadhyay, and K. Roy, Purdue
University, West Lafayette, IN
We analyze the impact of surface
orientation on stability, performance and power of 6-T and 8-T FinFET SRAMs. We
show that, in comparison to 32nm 6-T FinFET SRAM cell with devices of (110)
orientation, multi-oriented devices with optimized orientation can improve the
static noise margin (SNM) by 23-35% and access time (~22-33%), while consuming
the same leakage power. For 8-T FinFET SRAM, multi-oriented devices can improve
write stability substantially (~17%) with negligible area
overhead.
10.4 -
10:00
Spreading
Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling (INVITED
PAPER), E. Ibe, S. Chung*, S. Wen*, H. Yamaguchi, Y. Yahagi,
H. Kameyama**, S. Yamamoto***, and T. Akioka**, Hitachi, Ltd.,
Recent diversity in multi-cell upset
(MCU) of CMOS SRAMs are reviewed and scaling effects are discussed. Single event upsets of 130nm SRAM are
examined under high energy neutron irradiation. Novel MCU features, in which
errors can be corrected by re-writing but Idd increases stepwise depending on
MCU multiplicity, were identified with very high dependency of MCU features on
data patterns. MCBI (multi-coupled bipolar interaction) mechanism is proposed by
the authors to elucidate the features fully.
10.5 -
10:50
Low
Cost Test of High Bandwidth Embedded Memories, K. Gorman, D.
Anand, G. Pomichter and W. Corbin, IBM Systems and Technology Group,
This work presents architectures and
methods necessary for providing efficient and thorough test of high bandwidth
embedded memories using low speed ATE. Details are also provided on the
techniques used to minimize test related silicon area and test time
requirements. This combination of flexible at-speed test with minimal circuitry
and ATE requirements, and reduced time under test, leads to lower cost
production of embedded memories.
10.6 -
11:15
High-Temperature,
High Reliability EEPROM Design For Automotive
Applications, J. Walsh and G. Scott, AMI Semiconductor,
An EEPROM has been developed capable
of extreme temperature ranges not currently available in the industry. The
memory is expected to handle 100K write cycles, 10K of which can be at 175C. To
accommodate the reliable operation at the extreme temperature and write-cycle
conditions without adding steps to the base process, several cell and system
level design techniques were implemented including a differential bit
architecture, time and temperature program voltage shaping.
10.7 -
11:40
Self-referenced
sense amplifier for across-chip-variation immune sensing in high-performance
Content Addressable Memories, I. Arsovski and R. Wistort, IBM Silicon Solutions,
Essex Junction, VT
A memory sense-amplifier
self-calibrates during sense-line precharge to reduce signal development and
minimize timing uncertainty caused by random device variation. Compared to
conventional single-ended sensing, this method reduces sense-time by 70% while
also decreasing sense-power by 40%. The self-referenced sensing scheme is
implemented in a 64x240bit Content Addressable Memory (CAM) testchip. Fabricated
in 1V 65nm CMOS, this scheme achieves 2.2ns search-access on a 240bit
Session
11 – Emerging Technologies: Materials and
Structures
Tuesday
Morning, September 12
Fir
Ballroom
Chair:
Co-Chair:
11.1 -
8:05
Integrated
MEMS Switches for Leakage Control of Battery Operated
Systems, A. Raychowdhury, J. Kim, D. Peroulis and K. Roy,
Purdue University, West Lafayette, IN
This paper presents a novel and
efficient leakage control technique suitable for battery operated systems. In
this paper we propose to completely cut off the power supply of combinational
digital logic of the baseband processor in the standby mode of operation using
an integrated MEMS switch. Measurement results of thermally actuated MEMS
switches illustrate extremely low ON resistances (<3Ω) with
NO-standby power consumption. This methodology can drastically reduce the
leakage power, thereby increasing the battery lifetime by more than
50%.
11.2 -
8:30
CNT
based mechanical devices for ULSI memory, J. Jang, S. Cha, Y. Choi, D. Kang*, T. Butler, D.
Hasko, J. Kim** and G. Amaratunga, University of Cambridge, Cambridge, UK,
*Sungkyunkwan University, Suwon, Korea, Samsung Advanced Institute of
Technology, Yongin, Korea
Nanoelectromechanical (NEM) devices
were developed for memory. The concept of a switch unit employing carbon
nanotubes (CNT) was extended to random access memory (RAM). The unique vertical
structure of these nanotubes allows a high integration density for devices. Here
we report a NEM-dynamic random access memory (DRAM) based on the on the switch
and capacitor structures. The NEM-switch with lower driving voltage is also
extended to a unique design of static random access memory
(SRAM).
11.3 -
8:55
Nucleic
Acid Extraction, Amplification, and Detection on Si-based Microfluidic Platforms
(INVITED PAPER), L. Yobas, H-M.
Ji, W-C. Hui, Y. Chen, T-M. Lim*, C-K. Heng* and D-L. Kwong, Insitute of
This paper gives a brief overview of
silicon-based microfluidic platforms developed over the years by our group for
the extraction, amplification, and detection of the nucleic acids. Extraction of
both the genomic and viral nucleic acids from whole blood has been demonstrated
on Si-based microfluidics. Rapid amplification has been achieved by polymerase
chain reaction in Si-based thermal reactors (micro-PCR). Detection has been
realized by a chip-to-chip integration of the micro-PCR and micro capillary
electrophoresis (micro-CE).
11.4 -
9:20
Silicon
Integrated Circuits Including Antennas, K. O, K. Kim, B. Floyd, J. Mehta, H. Yoon, C-M. Hung,
D. Bravo, T. Dickson, X. Guo, R. Li, N. Trichy, J. Caserta,
The feasibility of integrating
antennas and required circuits to form wireless interconnects in CMOS
technologies is demonstrated. The key challenges including the effects of metal
structures in integrated circuits, heat removal, packaging, and interaction of
transmitted and received signals with nearby circuits appear to be manageable.
This technology can potentially be used for intra and inter-chip
interconnection, and implementation of true single chip radios, beacons, radars,
RFID tags and others, as well as contact-less testing.
Session
12 – Nyquist Analog-to-Digital
Converters
Tuesday
Morning, September 12
Pine
Ballroom
Chair:
David Nairn, Analog Devices
Co-Chair:
Nyquist analog-to-digital converters continue to push the
accuracy, speed and low-power boundaries by exploiting circuit techniques and
newer processing technologies.
12.1 -
8:05
Frequency-Based
Measurement of Mismatches Between Small Capacitors, A. Verma and B. Razavi,
The mismatch between two capacitors
can be measured by alternately switching each into an oscillator and measuring
the change in the oscillation frequency. Three-stage differential ring
oscillators can provide multiple mismatch data points for capacitances as small
as 8 fF. Experimental results obtained from test circuits fabricated in 0.13-um
CMOS technology also reveal lower mismatches for metal sandwich capacitors than
for lateral fringe structures.
12.2 -
8:30
A
Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with
High-Matching 3-D Symmetric Capacitors, Y-J.
Cho, K-H. Lee, H-C. Choi, S-H. Lee, K-H. Moon* and J-W. Kim*,
A 14b 70MS/s 3-stage pipeline ADC in
a 0.13um CMOS process employs signal insensitive 3-D fully symmetric capacitors
for high matching accuracy without any calibration scheme. The prototype ADC
with a 0.35um minimum channel length for 2.5V system applications shows measured
differential and integral nonlinearities of 0.65LSB and 1.80LSB at 14b, occupies
a die area of 3.3mm2, and consumes 235mW at 70MS/s.
12.3 -
8:55
A
3.5 GS/s 5-b Flash ADC in 90 nm CMOS, S. Park, Y. Palaskas*, A. Ravi*, R. Bishop* and M.
Flynn,
A 5-bit flash ADC incorporates
20µm-by-20µm inductors to improve both comparator pre-amplification bandwidth
and regeneration speed. A switched-cascode scheme reduces comparator kickback.
Offset cancellation is achieved by modifying the comparator reference voltages
without degrading high-speed performance. The ADC achieves a measured SNDR of
27.5dB for a 5MHz input at 4GS/s, and 23.6dB for a 1GHz input at 3.5GS/s. The
power consumption (including clock buffer and ladder) is 227mW at 3.5GS/s. The
active area is 0.658mm^2.
12.4 -
9:20
A
30-GS/sec Track and Hold Amplifier in 0.13-um CMOS
Technology, S. Shahramian, S. Voinigescu and A. Chan Carusone,
University of Toronto, Toronto, Canada
A 30-GS/sec CMOS track and hold
amplifier (THA) is designed and fabricated in a 0.13-um technology. The chip
operates from a 1.8-V supply and consumes 270 mW. The THA uses a switched source
follower topology. The measured single-ended S-parameters show an input and
output return loss of better than -10 dB up to 35 GHz and 7 GHz of bandwidth.
The measured total harmonic distortion of the THA is better than -29
dB.
12.5 -
10:00
A
10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting
Applications, Y-J.
Cho, D-H. Sa, Y-W. Kim, K-H. Lee, H-C. Choi, S-H. Lee, Y-D. Jeon*, S-C. Lee* and
J-K. Kwon*,
A 10b two-stage pipeline ADC
implemented in a 0.13um CMOS operates at dual sampling clock rates of 25MS/s and
10MS/s based on a switched-bias power-reduction technique for low-power system
applications. The prototype ADC shows a maximum SNDR and SFDR of 56dB and 65dB
at all sampling rates up to 25MS/s. The ADC occupies an active die area of
0.8mm2 and consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s, respectively, at a 1.2V
supply.
12.6 -
10:25
A
1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D
Converters, T. Ueno, T. Ito, D. Kurose, T. Yamaji and T. Itakura,
Toshiba Corporation,
This paper describes 10-bit,
80-MSample/s pipelined A/D converters for wireless-communication terminals. To
reduce power consumption, common-source, pseudo-differential amplifiers are used
in all the conversion stages. Common-mode disturbances are removed by the
proposed common-mode feedforward technique without using fully differential
amplifiers. The converter was implemented in a 90-nm CMOS technology, and it
consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are
58.6 dB and 52.2 dB, respectively.
12.7 -
10:50
Low-Power
Design of Pipeline A/D Converters (INVITED PAPER), S. Kawahito,
In this paper, low-power design
techniques of high-speed A/D converters are reviewed and discussed. Pipeline and
parallel-pipeline architectures are treated as these are dominant architectures
when required high sampling rate and high resolution with reasonable power
dissipation. A power optimization of pipeline and parallel pipeline ADCs based
on models of noise analysis and response time of a building block in the
multiple-stage pipeline ADC is also presented. Finally, the theoretical minimum of
required power in pipeline ADC is discussed.
12.8 -
11:40
A
1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS
ADC, J. Li,
X. Zeng, L. Xie, J. Chen, J. Zhang and Y. Guo*,
This paper describes a 10-bit 30-MS/s
subsampling pipelined ADC with a new configuration in the first stage that is
implemented in a 0.18 um CMOS process. The measured DNL and INL show less than
0.57 LSB and 0.8 LSB respectively. The ADC exhibits higher than 9.1 ENOB for
input frequencies up to 30 MHz and consumes 21.6 mW from a 1.8-V supply and
occupies 0.7 mm2, which also includes the bandgap and buffer
amplifiers.
Session
13 – Signal and Data Processing
Tuesday
Morning, September 12
Cedar
Ballroom
Chair:
Bryan Ackland, Noble Device Technology
Co-Chair:
Mobile computing and communications are primary market
drivers for today’s integrated circuit technology. Papers describe novel
techniques for providing improved communications and application signal
processing capability while maintaining low power
consumption.
13.1 -
8:05
Digital
Signal Processing for RF at 45-nm CMOS and Beyond (INVITED
PAPER), B. Staszewski, K. Muhammad and D. Leipold, Texas
Instruments, Dallas, TX
Having gained experience in
developing the first ever all-digital transmitter and digitally-intensive
receiver for mobile phones in 90-nm CMOS, we are offering in this paper our view
into the future of highly integrated RF circuits. First experimental designs in
45-nm CMOS reveal highly unfriendly environment for analog and RF circuits
design. The radio architecture to be successful must further transform the
conventional voltage domain into high-speed and high-precision operation of
predominantly digital circuitry.
13.2 -
8:55
Delta-Sigma
Modulation in Direct Digital Frequency Synthesis, D. Yang, W. Ni*, F. Dai, Y. Shi* and R.. Jaeger,
This paper presents comparisons of
various delta-sigma modulations in direct digital frequency synthesis.
Delta-sigma modulators such as MASH, feedforward, feedback and error feedback
have been implemented in both phase and frequency domains in a CMOS DDS. The DDS
prototype is fabricated in a 0.35um CMOS technology with core area of 1.7x2.1
mm2 and total 75 mA current. Measured DDS output demonstrates that frequency
domain delta-sigma modulation achieves better SFDR and SINAD than phase domain
delta-sigma modulation
13.3 -
9:20
OFDM
modulator with digital IF and on-chip D/A-converter, J. Lindeberg, O. Väänänen, J. Pirkkalaniemi, M. Kosunen and K.
Halonen, Helsinki University of Technology, Espoo,
Finland
A digital OFDM modulator with
2048-point IFFT and 83.2MHz bandwidth is implemented. The modulator consists of
IFFT block, upsampling filters, upconversion included in the upsampling
operation, a clipping unit, and on-chip D/A-converter. The clipper is used to
efficiently utilise the whole dynamic range of the converter and to maximise the
power efficiency of the power amplifier. The digital IF signal is converted to
analog signal by using a 10-bit on-chip D/A-converter with sampling frequency of
819.2MHz and center frequency of 204.8MHz.
13.4 -
10:00
Neuromorphic
Vision Systems for
Neuromorphic vision systems are ideal
for mobile applications because they promise compact computational sensing at
lower power consumption compared to the traditional imager/ADC/CPU systems.
These properties are particularly important for unmanned aerial vehicles. We
present current-mode low noise imaging, which is typically difficult to realize,
and computation-on-readout imaging processing for stereopsis and motion
estimation. We discuss how these processed images can be used for guiding and
controlling mobile robots.
13.5 -
10:25
A
Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics
Systems, B-G.
A low-power, area-efficient
multifunction arithmetic unit has been developed for programmable shaders for
handheld 3-D graphics systems. It adopts the logarithmic number system at the
arithmetic core for single cycle throughput and small-size low-power unification
of various vector and transcendental operations. An uneven 24-piecewise
logarithmic conversion scheme is proposed with maximum 0.8% conversion error. A
93K gate test chip is fabricated with 0.18-µm CMOS technology. It operates at
210MHz with 15.3mW power consumption at 1.8V.
13.6 -
10:50
A
Programmable Security Processor for Mobile
System-on-Chips, S. Ravi, A. Raghunathan, M. Sankaradass and S.
Chakradhar, NEC Laboratories America, Princeton,
NJ
We present a programmable security
processor customized to efficiently execute a wide range of symmetric, hashing,
and public-key cryptographic algorithms. It has been implemented in four
commercial SoCs, including a mobile application processor in 0.13um CMOS
technology. The security processor at 100MHz achieves processing rates of
24.7-91.4Mbps for symmetric encryption, 295-371Mbps for hashing, and 149.5ms for
1024-bit modular exponentiation, with a power consumption of
19mW.
13.7 -
11:15
A
Scalable 7.2 Mb/s 3GPP HSDPA Co-processor with Advanced NLMS Receiver and
Receive Diversity for Mobile Terminals, C. Thomas, M. Cooke, O. Ridler, K. Van Den Beld, D.
Yip, U. Sontowski, A. Kind, G. Zhou, Y-C. Li, L. Ung, R. Banna, B. Widdup, T. Prokop, M. Bickerstaff, G.
Woodward, R. Srikantiah*, K. Gupta*, R. Reddy*, S. Arvapalli*, R. Bidnur*, P.
Avss*, R. Lang, C.
An HSDPA co-processor for 3G mobile
terminals performs all layer 1 baseband chip rate, symbol rate, physical channel
and transport channel processing required to receive 3GPP Release 6 HSDPA at
data rates up to 7.2 Mb/s. The design is scalable to all HSDPA data rates up to
14 Mb/s. An advanced receiver using NLMS adaptive equalisers and receive
diversity provides up to 6.4 dB better performance than a traditional single
antenna RAKE receiver.
13.8 -
11:40
A
GFLOPS Vector-DSP for Broadband Wireless Applications, E. Matus, H. Seidel, T. Limberg, P. Robelly and G.
Fettweis, Dresden University of Technology, Dresden,
Germany
In this paper the low-power
high-performance floating-point vector DSP (SAMIRA) is presented primarily
intended for base-band signal processing applications. SAMIRA DSP is build upon
0.13um UMC technology running at a maximum clock frequency of 212MHz. The
processor combines SIMD and VLIW parallelism and it represents the first silicon
prototype based on synchronous transfer micro-architecture (STA). The
implementation results demonstrate the quantitative performance of the
processor.
Session
14 – Design for Test and Reliability
Tuesday
Morning, September 12
Fir
Ballroom
Chair: Hamid Mahmoodi,
Co-Chair:
Architecting
reliability is the focus of the first two invited papers, followed by a paper on
capturing supply noise, another on at-speed structural test, concluding with a
paper on improving EM-robustness in inductors.
14.1 -
10:00
SRAMs
in Scaled Technologies under Process Variations: Failure Mechanisms, Test &
Variation Tolerant Design (INVITED), S. Mukhopadhyay, A. Agarwal, Q. Chen and K. Roy,
Inter-die and intra-die variations in
process parameters can lead to large number of failures in an SRAM array,
thereby, degrading the design yield in nanometer technologies. In this paper, we
analyze and model different mechanisms of SRAM failures due to parameter
variations, and discuss test methodologies to detect such failures. We also
describe self-repairing techniques – one circuit level (using adaptive body
biasing) and one architecture level (using Built-in-self-test, redundancy and
address remapping) - to improve parametric yield of SRAM.
14.2 -
10:25
The
UltraSPARC T1 Processor: CMT Reliability (INVITED), A. Leon, B. Langley and J. Shin, Sun Microsystems
Inc.,
The first generation of "
14.3 -
10:50
A
Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and
Power Supply Voltage Drop, T. Sato, Y. Matsumoto, K. Hirakimoto, M. Komoda and J.
Mano, Renesas Technology Corporation, Tokyo, Japan
A time-slicing ring oscillator (TSRO)
which captures dynamic delay degradation due to instantaneous voltage drop on a
power supply network is proposed. Voltage drop impact on delay is directly
measured and time-domain effective voltage drop waveforms is also obtained. The
TSRO consists of standard logic cells only hence fits almost anywhere in logic
circuits for in-situ measurements. Measurement results of a test chip using
90-nm process successfully proved its concept.
14.4 -
11:15
Design
For At-Speed Structural Test And Performance Verification Of High-Performance
ASICs, V. Iyengar, M. Johnson, T. Anemikos, G. Grise, M. Taylor, R. Farmer, F.
Woytowich and B. Bassett, IBM Microelectronics,
Performance verification is critical
to high-performance ASICs manufacturing. Performance verification ensures that
only those chips whose performance is higher than an advertised threshold are
shipped to demanding customers. This provides a means to weed out nominal
performance ASICs, and also ship ASICs at difference grades. At-speed structural
test can provide performance verification capability at very low cost. In this
paper, we present a scalable and flexible structural test method for performance
verification of ASICs. The proposed method requires no tight restrictions on the
circuit design. Moreover, low-cost testers are used, thus sharply reducing test
cost.
14.5 -
11:40
Robust
Inductor Design for RF Circuits, Y-L.
Lu, Y-H. Lee, W. McMahon and T-C. Fung, Intel Corporation,
Design of monolithic spiral inductors
with electromigration (EM) robustness has been demonstrated. By adding small
metal reservoir structures in the underpass area, inductor EM lifetime can be
significantly improved. Measurements showed that the metal reservoir structures
do not have an impact on inductor Q and inductance. Adding these structures
hence allows more aggressive and scalable RF IC design.
Session
15 – SoC/SiP 3-D Power/Signal transport and
MEMS/Sensors Management
Tuesday
Afternoon, September 12
Oak
Ballroom
Chair:
Co-Chair:
Novel
techniques for SoC/SiP are presented which include
wireless power transmission and high density through die vias for SiP, a photo diode
interface for automotive, and a high voltage generator for
MEMS.
15.1 -
2:05
Chip-to-Chip
Inductive Wireless Power Transmission System for SiP
Applications, K. Onizuka, H. Kawaguchi*, M. Takamiya, T. Kuroda**
and T. Sakurai,
A chip-to-chip inductive wireless
power transmission system is proposed and the feasibility is experimentally
demonstrated for the first time. The circuit realized 2.5mW power transmission
at the output DC voltage of 0.5V using 700x700µm on-chip planar inductors for
the transmitter and the receiver. Methods to optimize the circuit design about
the maximum transmission power and the simulated optimization results are
discussed.
15.2 -
2:30
Balanced
Low Noise High Dynamic Photodiode Interface for
Automotive, I. Koudar, AMIS Mixed
A high performance balanced
photodiode sensor interface for the automotive industry is introduced. A novel
switched current based architecture provides 100dB input current dynamic range.
Correlated double sampling technique is used for 1/f noise suppression in the
MOS input circuitry. Sigma Delta ADC (13 bit) is used. The measured SNR is
>66dB. Embedded offset compensation supports fast 236us conversion cycle per
channel. Mixed signal chip architecture is described. EMC emissions meets a
strict automotive limits.
15.3 -
2:55
On-chip
Digitally Tunable High Voltage Generator for Electrostatic Control of
Micromechanical Devices, L. Aaltonen, M. Saukoski and K. Halonen, Helsinki
University of Technology, Finland
Micromechanical structures with
capacitive readout provide a feasible alternative for feedback by utilizing
electrostatic forces without any requirement for additional electrodes. This
paper presents circuit structures for on-chip high voltage generation. A high
voltage amplifier with digitally controllable output is implemented and, as an
example application, the DAC is used for quadrature compensation of a
microelectromechanical gyroscope. The implemented high voltage generator
achieves output voltages between zero and 27 V in 29 mV
steps.
15.4 -
3:20
Die
Stacking Technology for Terabit Chip-to-Chip
Communications, A. Rahman, J. Trezza*, B. New and S. Trimberger,
Xilinz Research Lab,
In this paper a die stacking
technology, leveraging on through die via (TDV) integration and wafer bonding,
is presented. Using state-of-the-art volume manufacturing environment, 10:1
aspect ratio TDV and wafer-level bonding technology are developed and initial
electrical and reliability characterization of TDVs are provided. The
opportunities for die-stacking technology to alleviate chip-to-chip
communication bottleneck are discussed and visions for stacked-die applications,
utilizing a programmable virtual backplane, are presented.
Session
16 – Eye-Opening Circuits
Tuesday
Afternoon, September 12
Fir
Ballroom
Chair:
Co-Chair:
This
session focuses on CMOS wireline transceiver building
blocks. A tutorial on transmit
equalization and two novel clock and data recovery architectures are
described.
16.1 -
2:05
Wireline
Equalization using Pulse-Width Modulation (INVITED
PAPER), J. Schrader, E. Klumperink, J. Visschers* and B.
Nauta,
High-speed data links over copper
cables can be effectively equalized using pulse-width modulation (PWM)
pre-emphasis. This provides an alternative to the usual 2-tap FIR filters. The
use of PWM pre-emphasis allows a channel loss at the Nyquist frequency of ~30dB,
compared to ~20dB for a 2-tap symbol-spaced FIR filter. The PWM filter has only
one ‘knob’ which is the duty-cycle. Two transmitter chips were tested with
differential and coaxial cables. A bit rate of 5 Gb/s (2-PAM) was achieved with
all cable assemblies, over a cable length of up to 130 m, with BER
<10^-12.
16.2 -
2:55
A
10Gbps Burst-Mode CDR Circuit in 0.18um CMOS, C-F.
Liang, S-C. Hwu and S-I. Liu,
A 10Gbps burst-mode clock and data
recovery (CDR) circuit has been fabricated in 0.18 micron CMOS technology. It
recovers the input data and clock within 32 bits by using a gated
voltage-controlled oscillator, a quadrature generator and a phase-aligning loop
incorporating a half-rate bang-bang phase detector and a digital phase
interpolator. The measured peak-to-peak jitter of the recovered clock is
10.44ps. The die area is 1.73 x 2.01 mm2 and draw 200mw from a 1.8v
supply.
16.3 -
3:20
A
1.6Gbps Digital Clock and Data Recovery Circuit, P. Hanumolu, M. Kim,
G-Y.
Wei* and U-K. Moon,
A digital clock and data recovery
circuit employs simple 3-level digital-to-analog converters to interface the
digital loop filter to the voltage controlled oscillator and achieves low jitter
performance. Test chip fabricated in a 0.13um CMOS process achieves BER <
10^{-12}, +/-1500ppm lock-in range, +/-2500ppm tracking range, recovered clock
jitter of 8.9ps rms and consumes 12mW power from a single-pin 1.2V supply, while
operating at 1.6Gbps.
Session
17 – Analog Techniques
Tuesday
Afternoon, September 12
Pine
Ballroom
Chair:
Co-Chair:
Kathleen Philips, Philips Research
Speed
isn’t everything! This session
covers circuits with challenges in other dimensions including voltage
references, voltage regulators and high voltage
circuits.
17.1 -
2:05
A
Sub-1V Low-Noise Bandgap Voltage Reference, K. Sanborn, D. Ma and V. Ivanov*,
A sub-1 V bandgap voltage reference
is presented. The topology allows the reference to operate with low voltage
supply, by employing reverse bandgap voltage generation. It also has attractive
low-noise feature, without the use of any large external filtering capacitors.
Theoretical analysis and experimental results show that the output noise
spectral density is 40 nV/?Hz with a peak-to-peak output noise in 0.1 to 10 Hz
band of 4 µV. The
reference has a mean output voltage of 190.9 mV at room temperature. Temperature
coefficient of the reference voltage in ?40 °C to +125 °C range is 11 ppm/°C
(mean) with a standard deviation of 5 ppm/°C. The design is compatible with most
CMOS and BiCMOS fabrication processes.
17.2 -
2:30
A
Compact Programmable CMOS Reference With 40uV Accuracy, V. Srinivasan, G. Serrano, C. Twigg and P. Hasler,
Georgia Institute of Technology, Atlanta, GA
A compact programmable CMOS voltage
reference that is determined by the charge difference between two floating-gate
transistors is introduced in this paper. A prototype circuit has been
implemented in a 0.35um CMOS process; reference voltages ranging from 50mV to
0.6V have been achieved and initial accuracy of 40uV has been demonstrated as
well. Experimental results indicate a temperature sensitivity of approximately
53uV/dgC for a nominal reference voltage of 0.4V over a temperature range of
-60dgC to 140dgC.
17.3 -
2:55
A
Transient-Enhanced 20uA-Quiescent 200mA-Load Low-Dropout Regulator With Buffer
Impedance Attenuation, M. Al-Shyoukh, R. Perez and H. Lee*, Texas
Instruments Inc.,
This paper demonstrates a 200mA
low-dropout regulator (LDO) for portable applications. Buffer impedance
attenuation is developed to realize a single-pole loop response through shunt
feedback. The LDO is thus unconditionally stable without using an ESR zero and
output undershoots and overshoots are minimized during load transients.
Implemented in 0.35um twin-well CMOS, the LDO only dissipates 20uA quiescent
current. With a 1uF output capacitor, the maximum transient-output variation is
54mV with full-load step change of 200mA.
17.4 -
3:20
Compact
outside-rail circuit structure by single-cascode two-transistor
topology, A. Tamtrakarn, H. Ishikuro*, K. Ishida** and T.
Sakurai, University of Tokyo, Tokyo, Japan, Keio University, Yokohama, Japan,
Tokyo Institute of Technology,
This paper presents a new compact
outside-rail circuit structure for future scaled CMOS technology. The proposed
circuit is composed of only two transistors connected into a single cascode
style for increasing supply voltage to one more nominal supply voltage (VDD).
The circuit is manufactured and measured. Reliability is also verified by the
trajectory plot for gate-source voltage and gate-drain voltage of all devices.
The results confirm that triple of nominal supply voltage can be used without
any overstress in all CMOS devices. The proposed circuit saves 52% area and
improves speed for 40% of the conventional approach in the case of 4VDD. An
example of outside-rail opamp is also proposed by using the proposed
circuit.
Session
18 – Productivity Enhancement and Design
Optimization
Tuesday
Afternoon, September 12
Cedar
Ballroom
Chair:
Co-Chair:
Rob Jones, IBM
This
session presents the most important advances in compact models, simulation
algorithms, and web-based design methodologies for productivity improvement and
design optimization.
18.1 -
2:05
Enhancing
Productivity by Continuously Improving Standard Compact Models (INVITED
PAPER), J. Watts, IBM Mocroelectronic,
Industry standard compact models
enable a device designer to provide compact models to a circuit designer
regardless of the set of simulation tools used by that designer. The collaborative
process coordinated by the CMC ensures that the industry standard models are of
high quality and continue to evolve to meet the advancing needs of the
industry.
18.2 -
2:55
A
Web Tool for Interactive Exploration of Analog Design
Tradeoffs, C. Recker, B. Braswell, P. Drennan and C. McAndrew,
Freescale Semiconductor, Tempe, AZ
Financial concerns, design efficiency
needs, and new and complex phenomena in submicron technologies have created a
need for an analog design tool. Analog designers need tools that allow them to
be proactive and evaluate topology tradeoffs and promising approaches before
lengthy and laborious simulation work begins. This paper presents a web-based,
automated method where a designer can interactively explore analog design
tradeoffs, such as mismatch, gain, noise and other design parameters, across key
circuit blocks and devices.
18.3 -
3:20
Circuit
Optimization Using Scale Based Sensitivities, B.
Agrawal, F. Liu* and S. Nassif*,
IBM EDA,
In this paper we present a novel
technique for the efficient computation of circuit performance sensitivity in a
model independent manner. The advantage of our method is that it allows rapid
deployment of accurate optimization methods even for new or exploratory models.
We demontrate the use of these gradients in circuit optimization to generate an
area vs. timing variability trade-off curve for an SRAM cell design in the
presence of N and P device threshold voltage variations.
Session
19 – Panel Discussion
Session
20 – Panel Discussion
Tuesday
Afternoon, 4:00 pm – 5:30 pm
Session
21 –Custom Circuits
Wednesday
Morning, September 13
Oak
Ballroom
Chair: K.
Szajda, LSI Logic
The
session covers a number of applications ranging from current and voltage
effective generation to custom circuits used in optical sensor systems,MEMS and implantable
biomedical Microsystems.
21.1 -
8:05
A
4-Channel High-Precision Constant Current Control ASIC for Automotive
Transmission Applications, W. Horn, M. Graefling, G. Gross, M. Steiner, J.
Treiber, R. Dickman, and K. Reis, Infineon Technologies Austria AG,
Austria
An ASIC (application specific
integrated circuit) implementation of a 4-channel high precision, switched mode,
constant current controller is presented. The device is reliable and maintains
an output current accuracy of 1.5% in the automotive environment. A brief system
overview is presented with focus on the ASIC itself. The most important
requirements such as temperature range, common mode rejection, accuracy and
repeatability are discussed. The core circuits, such as bandgap reference and
input amplifier are shown in detail. An overview on the digital implementation
is presented and selected measurement results prove outstanding accuracy
performance under automotive conditions.
21.2 -
8:30
Dithering
Skip Modulator with a Width Controller for Ultra-wide-load
This paper proposes a
temperature-independent load sensor to decide the optimum power MOSFET width for
power saving of DC-DC converters. Besides, it also can decide the optimum
modulation technique in tri-mode operation, which is composed of pulse-width
modulation (PWM), pulse-frequency modulation (PFM), and a new proposed dithering
skip modulation (DSM). An efficiency-improving DSM operation is introduced to
raise the efficiency drop because of transition from PWM to PFM. Importantly,
DSM mode can dynamically skip the number of gate driving pulses, which is
inverse proportional to load current. Simplistically and qualitatively stated,
the novel load sensor can automatically select the optimum modulation method and
optimum power MOSFET width to achieve high efficiency over a wide load
range.
21.3 -
8:55
Per-Pixel
Floating-Point ADCs with Electronic Shutters for a
A per-pixel floating-point,
dual-slope ADC array for a 16x16 infrared detector array has been integrated in
a 0.18-um CMOS technology. To achieve a high dynamic range and high frame rate
simultaneously, an electronic shutter is combined with an ADC for each pixel. An
offset cancellation method, employing an integration capacitor, improves the
array uniformity. The prototype achieves a 19-bit dynamic range at 3kfps. Each
ADC consumes 7uW, occupies 4000um^2, and is well-suited to 3-dimensional
integration.
21.4 -
9:20
Smart
CMOS Charge Transfer Readout Circuit for Time Delay and Integration
Arrays, C.B. Kim, B-H.
Kim, Y.S. Lee, H. Jung and H.C. Lee, KAIST,
This paper presents a novel CMOS
charge transfer readout circuit for X-ray time delay and integration (TDI)
arrays with a depth of 64. By using charge transfer readout, the summing of the
signal charges easily implemented and the weakness of TDI arrays related to
defective pixels is solved by integrating a dead pixel elimination circuit. In
addition, the proposed method can be applied to a TDI arrays with large depths,
so a high signal to noise ratio (SNR) can be acquired.
21.5 -
10:00
A
104dB SNDR Transimpedance-based CMOS ASIC for Tuning Fork
Microgyroscopes, A. Sharma, F. Zaman and F. Ayazi, Georgia Institute of
Technology,
A CMOS ASIC has been designed and
interfaced with a high Q MEMS gyroscope to yield an angular rate sensor with a
1.2deg/hr noise floor and 2mV/deg/s rate sensitivity. A T-network based
transimpedance amplifier has been implemented with a measured capacitive
resolution of 0.04aF/rt(Hz), an SNDR of 104dB and which consumes ~400μW
of power. The TIA also provides large on-chip transimpedance and can sustain
oscillations in MEMS gyroscopes with motional impedances greater than
10MΩ.
21.6 -
10:25
Fully-Integrated
CMOS Power Regulator for Telemetry-Powered Implantable Biomedical
Microsystems, A. Sodagar, K. Wise, K. Najafi and M. Ghovanloo,
University of Michigan, Ann Arbor, MI
This paper reports a fully-integrated
multi-output CMOS power regulator designed for telemetry-powered implantable
microsystems. The requlator fabricated in a 1.5um standard CMOS process,
provides 5V, 3V, and 1.5V outputs, exhibits load regulation of as low as 5% when
delivering up to 17.3mA
load current, and demonstrates line regulation of as low as 0.3%/V over 1.8-V
input amplitude variation.
Session
22 – Oscillators
Wednesday
Morning, September 13
Fir
Ballroom
Chair:
Amjad Obeidat, National Semiconductor
Co-Chair:
Cormac O’Connell, Emerging Memory
Technologies
This
session presents advances in high-speed, widely-tunable voltage-controlled
oscillators and analysis of mutual pulling between
oscillators.
22.1 -
8:05
A
Varactor-Less 10GHz CMOS LC-VCO for Optical Communications Transceiver SOCs
Using Caged Inductors, A. Maxim, Maxim Inc.,
A 40% frequency range LC-VCO for
multi-standard optical communications SERDES SOCs was realized in 0.11 micron
CMOS. A virtually constant tuning gain was achieved by a variable capacitance
implemented with constant metal interconnect capacitors and FET voltage
controlled resistors. This varactor-less LC-VCO can be implemented in any
standard digital CMOS technology that has a thick metal option. The supply
pushing was reduced by balancing the positive voltage coefficient gate
capacitances with the negative voltage coefficient drain diffusion capacitances.
The tank inductor uses a metal cage to shield it from the noise radiated by the
digital side of the IC.
22.2 -
8:55
An
Ultra Compact Differentially Tuned 6GHz CMOS LC VCO with Dynamic Common-Mode
Feedback., B. Soltanian, H. Ainspan*, W. Rhee*, D. Friedman* and
P. Kinget, Columbia University, New York, NY, *IBM T.J. Watson Research Center,
Yorktown Heights, NY
A fully integrated 0.024mm^2
differentially tuned 6GHz LC VCO for 6+Gbps high speed serial (HSS) links in a
90nm bulk CMOS is presented. It is smaller than any LC-VCO reported to date at
this frequency. Its size is comparable with ring oscillators but it has
significantly better phase noise. A circuit technique is introduced to
dynamically set the common-mode (CM) voltage of the differential varactor
control signals equal to the VCO's CM. Using a differential control a very wide
tuning range from 4.5GHz to 7.1GHz (45%) is achieved. The VCO has a measured
phase noise of -117.7dBc/Hz at a 3MHz offset from a 5.63GHz carrier while
dissipating 14mW from a 1.6V supply.
22.3 -
9:20
Mutual
Injection Pulling Between Oscillators, B. Razavi,
This paper proposes a theory for the
behavior of free-running or phase-locked oscillators that experience mutual
injection pulling. The time- and frequency-domain responses are derived for each
case and the profile of the resulting sidebands is calculated analytically.
Experimental results obtained for two 1-GHz CMOS PLLs that are resistively
coupled on-chip are presented.
Session
23 – Advanced Technology Developments and Fabrication
Challenges
Wednesday
Morning, September 13
Pine
Ballroom
Chair:
Co-Chair:
Advanced Technology Developments & Fabrication
Challenges
Abstract: This session of Invited papers covers CMOS scaling, advanced structures and packaging for high-performance digital and RF applications, as well as competing technologies that overcome present-day limitations of conventional CMOS.
23.1 -
8:05
Technologies
for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges
(INVITED PAPER), S. Decoutere, P. Wambacq, V. Subramanian, J. Borremans and A. Mercha, IMEC,
New process modules and device
architectures emerging for (sub-) 45nm CMOS lead to both opportunities and
challenges for analog/RF design. These will be discussed at the device and
circuit level for two competing architectures (planar bulk versus FinFETS), for
different gate stacks. FinFETs will be shown to be better suited for analog
baseband design while maintaining acceptable RF performance in the 1-10 GHz
range, while planar bulk CMOS outperforms the FinFETs for circuits above 10
GHz.
23.2 -
8:55
Recent
Advances in III-V Electronics (INVITED PAPER), Y-K.
Chen, Y. Baeyens, N. Weimann, J. Lee, J. Weiner, V. Houtsma, Y. Yang, Lucent
Technologies, Murray Hill, NJ
Compound III-V semiconductor circuits
promise fast and power efficient analog, digital and mixed-mode applications.
This paper will provide an overview of recent advances in high speed III-V
compound devices and integrated circuits for high capacity wireless and optic
fiber communications. Several critical compound semiconductor ASIC technologies
and their unique performance advantages over prevailing silicon CMOS and SiGe
technologies will be illustrated.
23.3 -
10:00
Electrical
Characteristic Fluctuations in Sub-45nm CMOS Devices, F-L.
Yang, J-R. Hwang and Y. Li*, TSMC,
Random fluctuations of electrical
characteristics in sub-45nm CMOS devices introduced by process-parameter
variations through severe short channel effects have made the scaling of
conventional planar transistors much more difficult than ever before, especially
while further reduction of gate dielectric thickness is ambiguous. In this
paper, we systematically investigate the fluctuations of threshold voltages at
varied gate length, considering the effects of channel doping, gate dielectric
thickness, and new transistor structures such as thin-buried-oxide SOI and
FinFETs. Quantitative analysis is undertaken in terms of three major variation
sources: random doping distribution, gate length deviation, and line edge
roughness. The analysis also features a low Vt-fluctuation transistor for 16nm
node achieved with undoped body, mid-gap metal gate, and nanowire
channel.
23.4 -
10:25
SiGe
BiCMOS Trends - Today and Tomorrow (INVITED PAPER), J. Dunn, D. Harame, A. Joseph, S. St. Onge, N.
Feilchenfeld, L. Lanzerotti, E. Gebreselasie, J. Johnson, D. Coolbaugh*, R. Rassel and M.
Khater**, IBM, Essex Junction, VT,
*
High performance communications
applications have made technology choices more important than ever. Silicon
Germanium (SiGe) BiCMOS has enabled the widespread introduction of many these
applications by providing superior cost and integration capability, compared to
III-V solutions and, relative to RFCMOS, one can attain better time to market.
BiCMOS integration approaches for high performance and cost performance NPN
modules as well as state of the art passive elements are
discussed.
23.5 -
11:15
Advances
and Challenges in Flip-Chip Packaging (INVITED PAPER), R. Mahajan, D. Mallik, R. Sankman, K. Radhakrishnan,
C-P. Chiu and J. He, Intel Corporation,
The role of semiconductor packaging
has evolved from space transformation and environmental protection, to becoming
an important enabler for silicon and system performance. This paper will examine
some of the advances in flip-chip packaging as an enabler of power delivery and
power removal using a microprocessor as an example. In addition, the role of the
package as an enabler of system I/O performance and silicon back-end reliability
will be examined.
Session
24 – Modeling for RF
Wednesday
Morning, September 13
Cedar
Ballroom
Chair:
Colin McAndrew, Freescale Semiconductor,
Inc.
Co-Chair:
This
session presents developments in modeling of noise, inductors and gate
resistance in advanced RF processes, and new research in injection-locked
oscillators.
24.1 -
8:05
Compact
modeling of noise in CMOS (INVITED PAPER), A. Scholten, R. van Langevelde, L. Tiemeijer and D.
Klaassen, Philips Research Europe, Eindhoven, The
Netherlands
The physical background of the
thermal noise equations of the PSP MOSFET model [1] is presented. The PSP
thermal noise model is shown to pass a number of proposed benchmark tests for
MOSFET thermal noise. Without any fitting parameters, it is shown to predict
with great accuracy a collection of experimental data on three modern CMOS
technologies. The impact of device layout on noise properties is discussed and
demonstrated experimentally.
24.2 -
8:55
A
Scalable Model Methodology for Octagonal Differential and Single-Ended
Inductors, V. Blaschke and J. Victory, Jazz Semiconductor,
Scalable models for circuit design
components such as inductors are a requirement for state of the art design
environments. Octagonal inductors are preferred over square inductors due to
their higher Q factor. In this paper we present a model methodology for
broad-band scalable octagonal inductors. Measurement data and electromagnetic
simulation results are presented to demonstrate the accuracy of the
model.
24.3 -
9:20
Measurement
of Inductive Coupling Effect on Timing in 90nm Global
Interconnects, Y. Ogasahara, M. Hashimoto and T. Onoye,
Inductive coupling is becoming a
design concern for global interconnects in nano-meter technology. This paper
shows measurement results of inductive coupling effect on timing, and reveals
that inductive coupling noise is a practical design issue in 90nm technology.
The measured delay change curve is consistent with circuit simulation results
with RLC interconnect model, and definitely different from those of conventional
RC model. Long-range effect and noise reduction by ground insertion are clearly
observed on silicon.
24.4 -
10:00
A
Novel Monitoring Method of RF Characteristics Variations for Sub-0.1um MOSFETs
with Precise Gate-resistance Model, A. Tanabe, K. Hijioka and Y. Hayashi, NEC Corporation,
Kanagawa, Japan
RF characteristics for sub-0.1um
MOSFETs such as ft, fmax and their variations are estimated from the DC and
capacitance parameters. A new RF gate resistance model with a
silicide-polysilicon interface resistance is a key factor to estimate the RF
characteristics precisely. The variations of RF characteristics are also
inferred from correlation coefficient between the RF parameters and the
DC/capacitance parameters. This method is effective in monitoring RF
characteristics and their variations for scaled-down, RF/mixed-signal
circuits.
24.5 -
10:25
Sizing
Ground Taps to Minimize Substrate Noise Coupling in RF
LNAs, A. Sundaresan, T. Fiez and K. Mayaram,
The influence of the sizing of ground
taps on the noise injected into a 1.5GHz low noise amplifier (LNA), by a stepped
buffer, for a heavily doped CMOS process is quantitatively examined. Precise
modeling provides good agreement between measurements and simulations. A 10dB
increase in isolation was achieved by scaling the area of the substrate contact
by a factor of 400, and by increasing the proximity of the contacts to the
sensitive transistors.
24.6 -
10:50
First-Harmonic
Injection-Locked Ring Oscillators, B. Mesgarzadeh and A. Alvandpour,
This paper presents an analysis of
first-harmonic injection locking in CMOS ring oscillators. In this analysis,
Adler’s equation is proved by using a new analytical approach based on the
propagation delay of an inverter stage. Also the behavior of the
injection-locked ring oscillators from phase noise point of view is discussed
and a closed-form equation for the phase noise of such oscillators is derived.
According to the measurement results on a DLL-based frequency multiplier
implemented in 0.13-micron CMOS process, good agreement between theoretical
prediction and measurements is observed.
24.7 -
11:15
Analysis
of Oscillators Locked by Large Injection Signals: Generalized Adler's Equation
and Geometrical Interpretation, A. Mirzaei, M. Heidari and A. Abidi,
Using the hard-limiting
characteristics of transconductors, a new model for injection-locking,
applicable for any strong and weak injection, is proposed. Backed by
simulations, examples of the powerfulness of this new model are enumerated as
proof of the concept.
24.8 -
11:40
Rigorous
Analytical/Graphical Injection Locking Analysis of Two-Port Negative Resistance
Oscillators, T. Mei and J. Roychowdhury, University Minnesota, Twin
Cities, MN
In this paper, we present a simple
but rigorous nonlinear analysis for understanding and predicting steady-state
operation and injection locking in two-port nonlinear negative-resistance
oscillators (such as the Colpitts, Pierce, etc., topologies commonly used in
RFICs). Key advances of our approach include the use of vector-based nonlinear
feedback analysis and treatment of amplitude and frequency components in a
coupled way. We develop rigorous and insightful graphical approaches for output
voltage estimation and injection lock range prediction. We validate our
analytical approach against transient and harmonic balance
simulations.
Session
25 – PLLs and DLLs
Wednesday
Morning, September 13
Fir
Ballroom
Chair: Eric
Naviasky, Cadence
Co-Chair:
This
session covers advances in the design of low noise/spurious PLLs and DLLs for frequency generation and clock
recovery.
25.1 -
10:00
A
Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock
Recovery, TY. Oh, S-H. Yi, S-H Yang, B-C. Lim and K-T. Hong, LG
Electronics,
This paper presents a digital PLL for
low long-term jitter clock recovery. A jitter reduction scheme for digitally
controlled oscillator is proposed and 39% jitter reduction is observed. A
5-phase digital phase frequency detector has 265 ps resolution and controls
output clock phase by 132 ps step. The long-term jitter is measured as 460 ps
pk-pk. This digital PLL is implemented in 0.18 µm CMOS process using 0.417 mm^2
and consumes 61.0 mW power.
25.2 -
10:25
Adaptive-Bandwidth
Mixing PLL/DLL Based Multi-Phase Clock Generator for Optimal Jitter
Performance, A.Tan and G-Y. Wei,
This paper presents an
adaptive-bandwidth mixing PLL/DLL (MX-PDLL) based multi-phase clock generator
that can operate as a PLL, DLL, or a mixture of the two. Moreover, this clock
generator can be used in a proposed dual-loop CDR to minimize output clock
jitter under various noise environments. A test-chip prototype of the MX-PDLL
and a 360ş phase rotator was fabricated in a 0.18μm CMOS process,
operating off of a 1.8V supply. Experimentally measured results verify that
while PLL-mode operation offers the ability to better filter quantization noise
from the digital CDR control, shifting towards DLL-mode operation offers the
ability to reduce jitter as the amount of on-chip noise
increases.
25.3 -
10:50
A
Low Jitter Multi-Phase PLL with Capacitive Coupling, J.Y. Park and M. Flynn, University of Michigan, Ann
Arbor, MI
Capacitive coupling improves both
phase noise and phase accuracy in coupled LC oscillators since the coupling
current is in phase with the regeneration current. A prototype 3 GHz PLL with
four LC oscillator stages and capacitive coupling is fabricated in
0.13m CMOS. The long term measured RMS jitter of the buffered clock
from the PLL is 1.61ps and the pk-pk jitter is 13.33ps.
25.4 -
11:15
A
150MHz-400MHz DLL-Based Programmable Clock Multiplier with -70dBc Reference Spur
in 0.18um CMOS, P. Maulik and D. Mercer, Analog Devices,
This paper describes a 0.18um CMOS
programmable clock multiplier which uses a recirculating DLL to achieve 1ps-5ps
RMS jitter and -70dBc reference spur level. It includes a sampling phase
detector and employs chopping, autozeroing and various other circuit techniques
to reduce static phase offset and crosstalk between the reference clock and the
output clock.
25.5 -
11:40
An
Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced
Spur, Q. Du, J. Zhuang and T. Kwasniewski,
This paper presents a new
programmable DLL based frequency multiplier with a period error compensation
loop designed to reduce the output spurious power level. The measurements show a
23 dB spur reduction from -23dB to -46.5dB at 1.216GHz is observed from the
measurement results. The measured cycle-to-cycle timing jitter at 2.16GHz is
1.6ps (rms) and 12.9 ps (pk-pk), and the measured phase noise is -110 dBc/Hz at
100 kHz off¬set.
Session
26 – Clocking and Data Recovery
Wednesday
Afternoon, September 13
Oak
Ballroom
Chair:
Co-Chair:
This
session presents novel GHz clock distribution techniques, low power oscillators,
and AC coupled interconnects.
26.1 -
1:35
Integrated
VCO Design for MICS Transceivers, A. Tekin, M. Yuce* and W. Liu, University of
California at Santa Cruz, Santa Cruz, CA, *The University of Newcastle,
Callaghan, Australia
The 402-405 MHz MICS (Medical Implant
Communication Service) band has recently been allocated by the US Federal
Communication Commissions (FCC) with the potential to replace the low frequency
inductive coupling techniques in implantable devices. This paper investigates
the designs of VCO (Voltage Controlled Oscillator) architectures that will be
essential building blocks of such wireless implantable devices. Three different
integrated quadrature VCOs that meet the requirements of the MICS standard are
designed in 0.18 um. TSMC CMOS process to propose an optimum choice. The
fabricated VCO’s are a four stage differential ring VCO, an LC tank VCO directly
loaded with a poly-phase filter and an 800 MHz LC tank VCO with a high frequency
master-slave divider. All three architectures target a VCO gain of Kvco = 15
MHz/V with 3 calibration control and 2 FSK (Frequency-Shift Keying) control
signals and are designed for 1.5 V supply voltage.
26.2 -
2:00
A
0.8V 1.52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference
for UHF RFID, R. Barnett and J. Liu*,
A low-voltage nano-power relaxation
oscillator for EPC standard UHF RFID transponder is presented. A low-voltage
inverted mirror feedback VGS/R reference is proposed to provide correlated
current and voltage references for the oscillator to meet the frequency
tolerance specification as well as meeting the proposed
Minimum-Supply-Voltage-Constraint design criterion to minimize the supply
voltage. Fabricated in 0.13 micron CMOS, the oscillator requires a minimum
supply voltage of 0.8V and consumes 400nA at 1.52MHz. The chip area is 13400
micron^2.
26.3 -
2:25
A
36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse
Receiver, L. Luo*, J.
Wilson, S. Mick, J. Xu,
L. Zhang, E. Erickson and P. Franzon,
A new differential pulse receiver is
demonstrated for AC Coupled Interconnect (ACCI), which enables the highest data
rate, at 6Gb/s/channel (36Gb/s ggregate), for capacitively coupled systems using
pulse signaling. The system works across FR4 printed circuit board (PCB)
interconnect lengths of up to 30cm with coupling capacitors from 95fF to 165fF,
while dissipating only 1.97mW/Gbps for the entire differential transceiver
(0.83pJ/bit for the transmitter & 1.23pJ/bit for the
receiver).
26.4 -
2:50
900MHz
to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and
Loading, J-Y.
Chueh, V. Sathe and M. Papaefthymiou,
A resonant clock network with
programmable driver and loading is designed in a 0.13µm CMOS technology. The
2mm×2mm distribution network has on-chip inductors and performs a forced
oscillation at the rate of a reference clock programmable in the 900MHz to
1.2GHz range. Clock amplitude and energy efficiency trade-offs at and off
resonance are explored with various driver configurations. Energy efficiency per
cycle is 1.39 to 1.56 times greater than previous resonant distribution
networks.
26.5 -
3:35
Clock
Generation and Distribution Using Traveling-Wave Oscillators with Reflection and
Regeneration, R. Wang, C-K.
Koh, B. Jung and W. Chappell,
We propose a novel traveling-wave
oscillator (R2TWO) that uses reflection and regeneration of waves on a
transmission line to generate multi-GHz square wave signals. We also propose a
scalable, low-power, low-skew and low-jitter clock distribution network by
tiling the basic R2TWOs in a regular fashion. Measurement results of a TSMC
0.18um CMOS test chip show that it can generate and distribute near full-swing
6.5GHz global clock signals with power saving of more than 75% (compared with a
traditional ring oscillator). The measured jitter is less than 0.84ps, and the
skew less than 1.3ps.
26.6 -
4:00
Injection-Locked
Clocking: A New GHz Clock Distribution Scheme, L. Zhang, B. Ciftcioglu, M. Huang and H. Wu,
University of Rochester, Rochester, NY
We propose a new GHz clock
distribution scheme, injection-locked clocking (ILC). This new scheme uses
injection-locked oscillators as the local clock regenerators. It can achieve
better power efficiency and jitter performance than conventional buffered trees
with the additional benefit of built-in deskewing. A test chip implemented in a
standard 0.18_um digital CMOS technology to distribute 5GHz clock through four
ILOs in an H-tree is demonstrated
Session
27 – Wireless Receivers
Wednesday
Afternoon, September 13
Fir
Ballroom
Chair:
Stefan Drude, Philips Semiconductors
Co-Chair:
In this
session implementations for advanced radio receivers will be presented, that
address the challenges of modern communication systems
.
27.1 -
1:35
Digital
RF Processor Techniques for Single-Chip Radios (INVITED
PAPER), B. Staszewski, K. Muhammad and D.
RF circuits for multi-GHz frequencies
have recently migrated to low-cost digital deep-submicron CMOS processes.
Unfortunately, this process environment, which is optimized only for digital
logic and SRAM memory, is extremely unfriendly for conventional RF designs. We
present fundamental techniques recently developed that transform the RF and
analog circuit design complexity to digital domain for a wireless RF
transceiver, so that it enjoys the benefits of digital approach, such as process
node scaling and design automation.
27.2 -
2:25
A
1.5V 0.7-2.5GHz CMOS Quadrature Demodulator for Multi-Band Direct-Conversion
Receivers, N. Poobuapheun, W-H. Chen, Z.
Boos* and A. Niknejad,
This paper presents an integrated
quadrature demodulator with on-chip frequency divider implemented in a 0.13 µm
CMOS technology. The mixer consists of a transconductor, a passive current
switching stage, and an operational amplifier output stage. A complementary
architecture has been used to increase the transconductance current efficiency.
From 0.7-2.5GHz, the demodulator achieves 10dB
27.3 -
2:50
A
1.5-V CMOS Receiver Front-End for 9-Band MB-OFDM UWB
System, S. Lou, H. Zheng and H. Luong, The
This paper presents the design of a
CMOS Receiver Front-End (RFE) with dual-conversion zero-IF architecture for
MB-OFDM UWB system covering the first 9 bands from 3.1 to 8.0 GHz. A 3-stage
wideband variable-gain LNA and a novel mixer with bottom LO input devices are
proposed. A fully integrated frequency synthesizer is included to generate the
desired LO signals with a band switching time of less than 1ns. Fabricated in
TSMC 0.18-µm CMOS process and operated at 1.5 V, the RFE measures a maximum
noise figure of 8.1 dB and an in-band IIP3 of -11.1 dBm while consuming a total
of 81.5 mA.
27.4 -
3:35
A
Distributed RF Front-End for UWB Receivers, A. Safarian, L. Zhou and P. Heydari, University of
California, Irvine, CA
This paper presents an UWB
distributed RF front-end (UWB-DRF) for UWB
IF-transceivers. It constitutes of merged LNA/mixer cells distributed
along artificial transmission lines, A 3-stage UWB-DRF was fabricated in 130nm
CMOS process, which achieves 15.5-13.8dB gain over UWB(3-10GHz) with almost flat
NF of 5.2-5.4dB. Programmable RF termination allows the UWB-DRF to achieve
higher gain of 17.7dB and lower NF of 3.5dB. The test chip draws 8.2mA from
1.8V, and occupies 1.5mm-square.
27.5 -
4:00
A
Fully-Integrated 0.11μm CMOS Digital Low-IF DVB-S2 Satellite TV Dual
Tuner SOC, A. Maxim, R. Poorfard, R. Johnson, P. Crawley, J. Kao,
Z. Dong, M. Chennam, T. Nutt and D. Trager, Silicon Inc., Nashua,
NH
A digital low-IF fully-integrated
dual tuner SOC for DVB-S2 satellite TV applications was realized in 0.11 micron
CMOS. It provides baseband digital I/Q outputs for a demodulator-on-host
back-end processor. A wide bandwidth ring oscillator based frequency synthesizer
having a large frequency step was used to down-convert a cluster of channels to
a sliding low-IF frequency, while the second down-conversion to baseband was
performed in the digital domain. The low-IF architecture allows a discrete AGC
loop, while avoiding 1/f noise and DC offset issues.
Session
28 – High Speed Analog
Wednesday
Afternoon, September 13
Pine
Ballroom
Chair:
Yusuf Haque, Maxim Integrated Products
Co-Chair: David Rich,
Consultant
This
session presents advances in on chip noise suppression, improvements on filter
tuning and linearity, temperature sensing techniques, dc and ac amplifier
performance and low noise oscillator.
28.1 -
1:35
Active
On-Die Suppression of Power Supply Noise, G. Keskin, X. Li and L. Pileggi, Carnegie Mellon
University, Pittsburgh, PA
An active on-chip circuit is
demonstrated in 130nm CMOS for the suppression of on-chip power supply noise due
to power distribution resonance. Testchip measurements indicate up to 40%
reduction in noise during clock/power gating at 2% power and 6% area overhead
cost. Oscillation time is reduced by 50%. Simulation results show that
comparable overshoot/undershoot and ringing control via on-chip decoupling would
require significantly more area and power due to leakage, particularly at 90nm
and below.
28.2 -
2:00
A
Fully Integrated DC/DC Converter for Tunable RF filters, M. Bouhamame, J. Tourret, L. Lococo, S. Toutain* and
O. Pasquier*, Philips
Semiconductors, Caen, France, *Institut de Recherche en Electronique et
Electrotechnique de Nantes Atlantique
A Controllable high voltage DC/DC
converter has been designed that can generate an output voltage from 0 to 30V
with a 2.8V supply voltage. It is suitable for controlling MEMS and high voltage
varicap devices in tunable filters. The proposed DC/DC converter uses a novel
approach to decrease the output voltage by cascading two Dickson charge pumps.
It is operating with a clock frequency of 16MHz and is built in a 0.25µm Bi-CMOS
technology.
28.3 -
2:25
A
Time Domain Mixed-Mode Temperature Sensor with Digital Set-Point
Programming, P. Chen, C-C.
Chen, T-K. Chen and S-W. Chen,
An accurate time domain mixed-mode
CMOS temperature sensor is proposed for on-chip temperature monitoring. A simple
delay line is utilized to generate the thermally sensitive delay time. A
succeeding multiplexer along with a reference delay line is used to program the
set-point. The chip area is merely 0.4mm2, the measurement error is ±0.8°C over
-40°C~95°C temperature range, the effective resolution is about 0.5°C, and the
power consumption is 9uW @ 20 samples/s.
28.4 -
2:50
A
Unity-Gain Buffer with Reduced Offset and Gain Error, G. Xing, S. Lewis* and T. Viswanathan**,
Marvell Semiconductor, *
A unity-gain buffer has been
fabricated in 0.35-micron CMOS technology. The circuit uses feed forward and
local feedback in a cascaded source follower circuit as well as two global
feedback loops: one to reduce the output resistance, gain error, and offset and
a second loop to further reduce gain error. The buffer consumes 3.7 mW at 3.3 V
and has a bandwidth of 92 MHz when driving a 13-pF capacitive
load.
28.5 -
3:35
A
19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18-um
CMOS, M. Hossain and A. Chan Carusone,
This paper describes a broadband CMOS
amplifier for differential receiver front-ends. A capacitive cross-coupling
network provides passive gm-boosting in the input cascode stage. This results in
a greater than 30% increase in bandwidth. Combined with several other
established bandwidth-enhancement techniques, the prototype achieves a measured
3-dB bandwidth of 19 GHz with no peaking in a 0.18-um CMOS process. The dc gain
is 11 dB differential, and the power consumption is 113 mW. Eye diagrams up to
24 Gb/s are shown.
28.6 -
4:00
A
0.6V Highly Linear Switched-R-MOSFET-C Filter, P. Kurahashi, P. Hanumolu, G. Temes and
U-K.
Moon,
The design and performance of a
switched-R-MOSFET-C filter is presented in this paper. The filter achieves -77dB
THD using a 0.6V supply, and -90dB THD using a 0.8V supply, with a 0.6Vpp
differential 2kHz sine input. High linearity at a low supply voltage is achieved
by the use of duty-cycle controlled tuning inside a feedback
loop.
28.7 -
4:25
Fast
Automatic Tuning of Channel Selection Filters Based on Phase Delay
Calibration, K. Kagoshima, S. Kawama, S. Toyoyama and K. Iizuka,
Sharp Corporation,
An automatic tuning method for
active-RC base-band filters used in direct conversion receivers is proposed.
Filter calibration is realized by setting the phase delay for a reference
frequency of 4.5 MHz to -360˚. The proposed method is accurate and area
efficient, since it does not require a replica filter but uses the filter
itself. In addition, monotonic control of the capacitor arrays makes fast tuning
possible.
28.8 -
4:50
A
Low Phase Noise 100MHz Silicon BAW Reference Oscillator, K. Sundaresan, G. Ho, S. Pourkamali and F. Ayazi,
Georgia Institute of Technology, Atlanta, GA
The paper presents a temperature
compensated 100MHz reference oscillator based on a capacitive Silicon Bulk
Acoustic Wave (BAW) resonator interfaced with a CMOS amplifier. The resonator is
optimized for high quality factor (92000) and low impedance. The CMOS IC
comprises of a trans-impedance amplifier to sustain oscillations and an oven
control mechanism for temperature control. A phase noise floor of -136dBc/Hz and
a temperature drift of 56ppm over 100°C were measured for the
oscillator.
Session
29 – Modeling and EDA Challenges in Nano-CMOS
Wednesday
Afternoon, September 13
Cedar
Ballroom
Chair:
Co-Chair:
This
session discusses and reviews modeling and EPA challenges in nano-scale CMOS technologies. The impact of variabilities on device and circuit performances will also
be covered.
29.1 -
1:35
EDA
Challenges in Nano-scale Technology (INVITED PAPER), J. Kawa, C. Chiang and R. Camposano, Synopsys, Inc.,
Since the onset of the 90nm node the
challenges associated with further transistor scaling while maintaining a
consistently functional, reliable, and yielding design has increased
exponentially. We expose and analyze a plurality of those challenges and go over
the solutions EDA tools are offering for dealing with them. We also look forward
and cover the future challenges associated with the integration of the emerging
bottoms-up nano-materials flow with the traditional equally-nano CMOS top-down
process flow.
29.2 -
2:25
Statistical
and Corner Modeling of Interconnect Resistance and
Capacitance, N. Lu, IBM Semiconductor Research and Development
Center, Essex Junction, VT
We describe an innovative and
comprehensive interconnect spice model for IBM 65 nm technology. The model links
the variability in the model to the variations in BEOL litho, deposition, etch,
and polish process steps, which is an industry first. It provides correct Monte
Carlo simulation results, offers correct corner modeling capability, and can
also generates a set of optimal interconnect corner models instantly without
running Monte Carlo simulations, which is another industry
first.
29.3 -
2:50
Experimental
Verification of Simulation Based Yield Optimization for Power-On Reset
Cells, G. Rappitsch, O. Eisenberger, B. Obermeier*, A. Ripp*
and M. Pronath*, austriamicrosystems AG, Unterpremstatten, Austria, *MunEDA
GmbH, Munich, Germany
Yield optimization of a
power-on-reset cell is performed by simulation based design centering. Critical
parameters are determined from sensitivity analysis enabling yield enhancement
by shifting of the production process. In a second step a new set of design
parameters is computed maximizing the worst-case-distance. The simulated yield
improvement for the initial design and the optimized design is verified by
electrical wafer testing under varying production conditions.
29.4 -
3:35
Measurement
results of delay degradation due to power supply noise well correlated with
full-chip simulation, Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato* and T.
Onoye, Osaka University, Suita, Japan, *Tokyo Institute of Technology, Yokohama,
Japan
Power integrity is an crucial design
issue in nano-meter technologies because of lowered supply voltage and current
increase. This paper focuses on gate delay variation due to power/ground noise,
and demonstrates measurement results in a 90nm technology. For full-chip
simulation, a current model with capacitance and variable resistor is developed
to accurately model current dependency on voltage drop. Measurement results are
well correlated with simulation, and verify that gate delay depends on average
voltage drop.
29.5 -
4:00
Delay
Variation Analysis in Consideration of Dynamic Power Supply Noise
Waveform, M. Fukazawa and M. Nagata,
Delay variability due to dynamic
power supply noise is elucidated by on-chip signal waveform measurements at
100-ps/100-uV resolutions applied to a 180-nm CMOS digital circuit. A
single-tone noise model represents a dynamic power supply noise waveform with
the most significant frequency component and leads to circuit-level simulation
that can efficiently capture the effects of switching signal waveform modulation
on delay in a logic gate. Simulation and measurements show excellent agreement
in delay variation, even with relative differences among clock domains in timing
as well as in noise strength. The proposed delay simulation technique actualizes
the delay analysis in consideration of dynamic power supply noise and thus
consolidates the timing closure especially in a high speed digital
design.
29.6 -
4:25
Crosstalk
Reduction with Nonlinear Transmission Lines for High-Speed VLSI
System, J. Kim, W. Ni and E. Kan,
We report efficient crosstalk and
signal reflection reduction with nonlinear transmission lines (NLTLs) for
high-speed VLSI. Crosstalk measurements of NLTLs implemented with the Lincoln
Lab 0.18 micrometer FDSOI (fully-depleted silicon-on-insulator) CMOS process are
performed in time domain as well as by S-parameters up to 25GHz. The excellent
suppression capabilities on signal reflection, data-dependent timing errors and
crosstalk without any circuit overheads in a broadband illustrate the advantage
of the NLTL global interconnect.
Posters
Monday, September
11
5:00 pm – 7:00
pm
P.01 -
A
Phase-Domain Continuous-Time 2nd-Order Delta-Sigma Frequency
Digitizer, M. Sharifkhani and M. Sachdev,
A frequency digitizer based on a
continuous time delta-sigma PLL is presented. The architecture combines the
demodulation and digitization process of a frequency modulated signal. This
operation is done at a high IF frequency with an excellent accuracy thanks to
the oversampling nature of the loop. Since the digitization occurs in phase
domain, the power consumption of the digitizer drops significantly compared to
the amplitude domain digitizers operating at the same
frequency.
P.02 -
A
CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background
Calibration, Z-M.
Lee, C-Y. Wang and J-T. Wu,
A 15-bit 125-MS/s time-interleaved
ADC is fabricated in a 0.18um CMOS technology, and achieves 91.9dB SFDR, 69.9dB
SNDR for a 9.99MHz input. The ADC uses a precharged sample-and-hold amplifier to
mitigate the performance requirements for its opamp. Digital background
calibration is applied to correct gain and offset mismatches between the
channels. Excluding I/O buffers, the chip occupies an area of 4.3mm x 4.3mm and
dissipates 909mW from a 1.8V supply.
P.03 -
A
Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback Buffer
Amplifier, W. Oh, B. Bakkaloglu, B.
Aravind* and S. K. Hoon*,
Low-noise, low-dropout (LN-LDO)
regulators are critical for supply regulation of deep-submicron analog baseband
and RF system-on-chip designs. A low 1/f noise LDO regulator utilizing a chopper
stabilized error amplifier is presented. In order to achieve fast response
during load transients, a current-mode feedback amplifier (CFA) with an
asymmetrical input pair is designed as a second stage. With chopping frequencies
up to 1MHz, an output noise spectral density of 32nV/√Hz and PSR of
38dB is achieved at 100kHz. Compared to an equivalent noise density static
regulator, the error amplifier silicon area is reduced by 75%. With the
current-mode feedback second stage buffer, settling time is reduced by 60% in
comparison to an equivalent power consumption voltage mode buffer, achieving 0.6
microsec settling time for a 50mA load step. The LN-LDO is designed and
fabricated on a 0.25 micron CMOS process with five layers of metal, occupying
0.88mm2.
P.04 -
10-b
100-MS/s Two-Channel Time-Interleaved Pipelined ADC, K. El-Sankary and M. Sawan,
Two-channel, 10-bit, 100-MS/s,
time-interleaved pipelined ADC designed and fabricated in 0.18 µm CMOS
technology is presented. Static gain mismatch between the channels is
compensated for by background correlation scheme. Dynamic gain mismatch is
reduced using skew-insensitive sampling in the first stage of every pipelined
ADC channel. Power consumption and chip area are minimized by using four-input
opamps sharing.This ADC achieves SNDR and SFDR of 57 dB and 69 dB
respectively.
P.05 -
A
20 GS/sec Analog-to-Digital Sigma-Delta Modulator in SiGe HBT
Technology, X. Li, W.-M. Kuo, Y. Lu and J. Cressler, Georgia
Institute of Technology,
This paper presents a monolithic
continuous-time 2nd-order analog-to-digital sigma-delta modulator implemented in
third-generation, 200 GHz SiGe HBT technology. The modulator can operate at a
sampling rate of 20 GS/sec with SNRs of 30.5 dB over a signal band from DC to
312.5 MHz, and 51 dB over 1 MHz bandwidth. Operating off a +3.5 V power supply,
the modulator dissipates a total of 490 mW. The die occupies an area of 1.58 ×
1.7 mm2.
P.06 -
A
300 C, 110-dB Sigma-Delta Modulator with Programmable Gain in Bulk
CMOS, X.Yu and S. Garverick,
A bulk CMOS, switched-capacitor
2nd-order sigma-delta modulator with pre-amplification uses correlated double
sampling, constant-gm biasing, and a modulator architecture with coefficients
adjusted to improve temperature stability. The stand-alone sigma-delta modulator
has a peak SNR and SNDR >= 94 dB and 87 dB, respectively, for temperature
from 25 C to 300 C with an oversampling ratio of 256. Including the
pre-amplifier, the modulator dynamic range is >= 110 dB at tempera-tures up
to 300 C.
P.07 -
A
0.18um CMOS 1000 frames/sec, 138dB Dynamic Range Readout Circuit for 3D-IC IR
Focal Plane Arrays, S. Kavusi, K. Ghosh, K. Fife and A. El Gamal, Stanford
University, Stanford, CA
A prototype of a new high dynamic
range readout scheme targeted for 3D-IC IR focal plane arrays is described.
Dynamic range is extended using synchronous self-reset while high SNR is
maintained using few non-uniformly spaced captures and least-squares fit to
estimate pixel photocurrent. The prototype comprises of a 16 x 5 readout pixel
array fabricated in a 0.18um CMOS process and achieves 138dB dynamic range and
60dB peak SNR at 1000 frames/sec with energy consumption of 25.5nJ per pixel
readout.
P.08 -
ViPro:
Focal-Plane Spatially-Oversampling CMOS Image Compression
Sensor, A. Olyaei and R. Genov,
The CMOS image sensor computes
spatially-compressing convolutional transforms directly on the focal plane,
yielding digital output at a rate proportional to the mere information rate of
the video. A bank of column-parallel Delta-Sigma-modulated analog-to-digital
converters (ADCs) performs distributed column-wise focal-plane oversampling of a
set of adjacent pixels and concurrent weighted average quantization. The number
of samples per pixel and switched capacitor sampling sequence order set the
amplitude and sign of the respective pixel coefficient. Outputs of a set of
adjacent ADCs are accumulated to realize a two-dimensional block matrix
transform in parallel for all columns. The 3.1 mm X 1.9 mm prototype, ViPro,
yields 4~GMACS computational throughput in real-time discrete cosine transform
(DCT) video compression when scaled to HDTV 1080i resolution.
P.09 -
Prediction
and Characterization of Frequency Dependent MOS Switch Linearity and the Design
Implications, T. Brown, M. Hakkarainen* and T. Fiez,
A proposed model predicts input
frequency dependent harmonic distortion in weakly nonlinear first order sampling
circuits. The math necessary to apply the model is greatly reduced to the
equivalent of frequency-independent nonlinearity analysis. Analytic expressions
for a MOS switch are derived. The first method to quantify the tradeoff between
thermally limited signal-to-noise ratio (SNR) and spurious free dynamic range
(SFDR) for sampling circuits is presented. Measured HD2-HD5 of a sample and hold
fabricated in a 1P5M 0.25um CMOS process support the
conclusions.
P.10 -
1.56
GHz On-chip Resonant Clocking in 130nm CMOS, M. Hansson, B. Mesgarzadeh and A. Alvandpour,
Linkoping University, Linkoping, Sweden
This paper describes a successful
experiment of 1.56 GHz on-chip LC-tank resonant clock oscillator, which drives
2x896 flip-flops, without intermediate buffers. Detailed power measurements of a
test-chip in 130-nm CMOS show that the resonant clocking results in 57% lower
clock power and 15-30% lower total power compared to the conventional clocking
on the same chip. Jitter measurements show a worst-case peak-to-peak jitter of
28.4ps across 0-to-80% data activity in the data-path.
P.11 -
Low-Ripple
CMOS Switched-Capacitor Power Converter With Closed-Loop Interleaving
Regulation, M. Somasundaram and D. Ma, The
This paper presents a new integrated
switched-capacitor (SC) power converter with an interleaving regulation scheme.
By dividing the original power stage into sub-units and operating each sub-unit
in an interleaving way, the converter achieves attractive low ripple voltage and
transient performance, without compromising other design parameters. The
closed-loop operation ensures accurate voltage regulation at any desired levels.
The design was fabricated with 0.35 um CMOS N-well process. The die area
including all pads and power transistors is 3.52 mm2. Measurement results show
that, with a supply voltage of 1.5 V and a load current of 250 mA, the output of
the converter is well regulated at 2.5 V with only 9-mV ripple. The maximum
efficiency of 82.3 % is achieved, when the output power reaches 625
mW.
P.12 -
A
Low Power ASK Clock and Data Recovery Circuit for Wireless Implantable
Electronics, H. Yu and R. Bashirullah,
This paper describes a low power
clock and data recovery (CDR) circuit with integrated ASK demodulator for
wireless implantable neural recording microsystems. A modulation scheme based on
amplitude shift-keying (ASK) and pulse position modulation (PPM) is employed to
simplify the complex-ity of implant circuits and reduce power transmission
require-ments. A charge-pump based CDR circuit is used to extract non-return to
zero data from the demodulated waveforms. A prototype has been fabricated in
2-poly 3-Metal 0.6µm bulk CMOS technology in order to validate circuit
functionality. The receiver front-end exhibits a sensitivity of 3.2mV p-p at
1MHz. The ASK demodulator and CDR operates over an input data range of 4kbs to
18kbs, measures 300µm by 600µm and dissi-pates 70µW from a 2.7V
supply.
P.13 -
An
Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast
Dynamic Voltage Scaling, J. Song, G. Yoon and C. Kim, Korea University, Seoul,
Korea
A fast adaptive digital DC-DC
converter for dynamic voltage scaling is presented. The control loop employs
coarse and fine controls for each power transistor to enhance output response
time and to reduce the conduction loss. The device was fabricated using a
0.18-㎛ CMOS process, occupying an area of 0.35mm2. The output voltage
can vary from 0.76V to 1.75V, with a resolution of 28mV/step and a tracking time
of 6.4㎲/V. Maximum efficiency of 94.8% is
achieved.
P.14 -
A
Floating-gate Based Low-Power Capacitive Sensing Interface
Circuit, S.-Y. Peng, M. Qureshi, A. Basu, P. Hasler and L.
Degertekin, Georgia Institute of Technology,
This paper describes a high SNR
capacitive sensing circuit topology based on a capacitive feedback charge
amplifier with high power & area efficiency. When the circuit is used in an
audio MEMS sensor, 78.6dB SNR in audio band is measured with less than 0.5 µW
power consumption. With a MOS-BJT pseudo-resistor feedback scheme, this topology
has also been applied to a capacitive micromachined ultrasonic transducer (CMUT)
operating around 1MHz.
P.15 -
PulseNet
-- A Parallel Flash Sampler and Digital Processor IC for Optical
SETI, A. Howard, G-Y.
Wei, W. Dally* and P. Horowitz,
PulseNet is a full-custom IC with
parallel flash ADC and digital processing that enables an all-sky optical search
for extraterrestrial intelligence. It integrates 448 sense amplifiers that
digitize 32 analog signals at 1GS/s, and other circuits that filter samples,
store candidate signals, and perform astronomical observations. Its ~250,000
CMOS transistors (TSMC 0.25um) dissipate 1.1W at 400MHz and
2.5V.
P.16 -
A
32Gb/s On-chip Bus with Driver Pre-emphasis Signaling, L. Zhang, J. Wilson, R. Bashirullah*, L. Luo, J. Xu and P.
A 16-bit on-chip bus with driver
pre-emphasis fabricated in 0.25um CMOS technology attains an aggregate signaling
data rate of 32Gb/s over 5-10mm long lossy interconnects while reducing delay
latency by 28.3%, power by 15.0%, and peak current by 70% over a conventional
single-ended voltage-mode static bus. The proposed bus is robust against
crosstalk noise and occupies comparable routing area to a reference static bus
design.
P.17 -
An
Integrated 90V Switch Array for Medical Ultrasound
Applications, R. Wodnicki, Y-M.
Li, N. Chandra and N. Rao, GE Global Research,
Abstract-An integrated 90V 16-channel
CMOS analog switch array has been designed and fabricated for next generation
medical ultrasound systems. The array was implemented in AMIS I2T100 technology;
the die area is 14.72mm^2. Measurement results show that the static power
consumption is 110uW. The on resistance of the switch is 200 Ohm, and the switch
off-state isolation is -30dB.
P.18 -
Towards
a Wearable Electronic Nose Chip, K-T.
Tang and R. Goodman*,
An electronic nose chip which uses
three carbon black polymer sensors as its input is fabricated and tested.
Results of longitudinal testing, response to analyte mixtures, temperature
dependence, and power dissipation are discussed in the paper. Future work
towards a fully integrated wearable electronic nose chip is discussed at the end
of the paper.
P.19 -
A
1V 420uW 32-channel Cortical Signal Interface, E. Lee, E. Matei, A. Lam and T. Li, Alfred Mann
Foundation,
A 32-channel cortical signal
interface with a 10-bit, 960kS/s ADC was designed to connect to a 121
microelectrode array. The 3.3-4V battery voltage was down converted to 1.0-1.3V
so that the amplifier biasing currents could be maximized to achieve low noise.
Native transistors and chopper stabilization were used to further reduce the
overall noise and offset. For each channel, a minimum input referred noise under
1.5µVrms was achieved with a maximum power consumption of
~13µW.
P.20 -
A
3D Multi-Aperture Image Sensor Architecture, K. Fife, A. El Gamal and
H.-S.
P. Wong,
An image sensor comprising an array
of apertures each with its own local integrated optics and pixel array is
presented. A lens focuses the image above the sensor creating overlapping fields
of view between apertures. Multiple perspectives of the image in the focal plane
facilitate the synthesis of a 3D image at a higher spatial resolution than the
aperture count. Depth resolution is shown to continue to improve with pixel
scaling below the diffraction limit. Preliminary circuit implementation is
described.
P.21 -
GHz
Serial Passive Clock Distribution in VLSI using Bidirectional
Signaling, V. Prodanov and M. Banu, MHI Consulting,
NJ
We introduce a serial passive clock
distribution technique for VLSI chips, allowing efficient and accurate skew
removal at any arbitrary clock drop point. The passive transmission medium may
be on-chip electrical transmission lines built in current IC technology or
possible optical wave-guides in future developments. The proposed technique is
naturally insensitive to practical loses and other non ideal effects and has the
capability of covering large chip areas.
P.22 -
A
Driving Scheme for AMOLED Displays Based on Current
Feedback, S. Ashtiani
and A. Nathan,
A scheme of driving AMOLED displays
with a-Si TFTs is presented. It provides fast programming and low sensitivity of
OLED current to VT shift of TFTs. The pixel circuit and column driver were
fabricated in an a-Si TFT process and a 0.8-um 20-V CMOS technology.
Measurements show less than 5% change in the OLED current for 2.5V shift in VT.
Settling times smaller than 70us were achieved for programming currents smaller
than 100nA.
P.23 -
Efficient
Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor
Networks, T. Le, K. Mayaram and T. Fiez,
An RF-DC power conversion system is
designed in a 0.25μm CMOS technology to efficiently convert RF energy
to DC voltages. The rectifier has 60% efficiency and can rectify input voltages
as low as 50mV by using floating gate transistors as rectifying diodes. For
distances of 15 meters, 1 volt DC is measured with 0.3μA load current
at 906MHz. The system operates with 5.5μW (-22.6 dBm) received power,
corresponding to 42 meters operating distance.
P.24 -
Match
Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable
Memories, N. Mohan, W. Fung, D. Wright and M. Sachdev,
University of Waterloo, Ontario, Canada
Match line sense amplifiers (MLSAs)
consume a significant portion of the total power in ternary content addressable
memories (TCAMs). In this paper, we present two MLSAs that employ positive
feedback techniques to reduce the power consumption. Energy measurement results
of the two MLSAs, fabricated with a 144x144 TCAM array in 0.18 micron CMOS
technology, show a reduction of 56% and 48% respectively over the conventional
current-race MLSA.
P.25 -
A
Soft-Error Tolerant Content-Addressable Memory (
Modern integrated circuits require
careful attention to the soft-error rate (SER) resulting from bit upsets, which
are normally caused by alpha particle or neutron hits. These events, also
referred to as single-event upsets (SEUs), will become more problematic in
future technologies. This paper presents a binary content-addressable memory
(
P.26 -
180nm
4Mb High Speed High Reliability Embedded SONOS Flash
Memory, L. Pan, D. Wu, G. Yang, L. Sun, H. Pang and J. Zhu,
Tsinghua University, Beijing, China
A 1.8/3.3V 4Mb (512K×8 bit) Embedded
SONOS flash memory has been successfully developed and verified with 180nm CMOS
logic compatible integrated technology, in which a reverse programming array
architecture and a novel high speed sensing circuit with dual-phase precharge
path and self-adjusted load are proposed to improve read speed. Moreover, a
novel threshold voltage tracking technique is also introduced to improve the
reliability. Finally, a 4.4mm2 core size and a 0.40micron^2 (12.4F2/bit) cell
size are obtained, and the test results show that the read speed and the
endurance characteristics are 17ns and 105, respectively.
P.27 -
A
Low-Power Routing Archictecture Optimized for Deep Sub-Micron
FPGAs, L. Ciccarelli, D. Loparco*, M. Innocenti*, A. Lodi*,
C. Mucci* and P. Rolandi, STMicroelectronics,
Signal propagation delay and leakage
power dissipation of FPGAs mainly depend on the routing architecture. In this
paper we propose solutions, which minimize the subthreshold current of the
switch and connection blocks. Our approach leads to a reduction of more than one
order of magnitude of standby leakage, up to 62% of active leakage of the
routing architecture, having a small impact on signal delay, without silicon
area increase.
P.28 -
A
0.13 μm Low-power Race-free Programmable Logic
Array, G. Samson and L. Clark, Arizona State University,
Tempe, AZ
A PLA using NAND and NOR gates for
the AND and OR logic planes, respectively, is described. The circuit design,
timing and power advantages are described. Nearly 50% power savings over a
conventional PLA design is achieved on a 130 nm process at less than 10% delay
cost. The new PLA circuit has been fabricated on a 130 nm low standby power
process and tested silicon operates at 905 MHz at VDD = 1.5
V.
P.29 -
An
Energy Scalable Computational Array for Sensor Signal
Processing, L. Guo, M. Scott and R. Amirtharajah,
Harvesting energy from environmental
sources can extend sensor node lifetimes beyond battery limitations. However,
scavenged energy is highly variable. We propose a computational array which
maximizes sensor performance by matching system power consumption to the
available energy through power scalable approximate signal processing. The array
consists of distributed arithmetic based functional units coupled with a
reconfigurable interconnect. Several sensor DSP applications have been mapped.
Post-layout simulations confirm the array is energy efficient and energy
scalable.
P.30 -
Nonlinear
Soft-Output Signal Detector Design and Implementation for MIMO Communication
Systems with High Spectral Efficiency, S. Chen, F. Sun and T. Zhang, Rensselaer Polytechnic
Institute,
VLSI implementations of nonlinear
MIMO signal detectors are not trivial, particularly for systems with high
spectral efficiency. For example, realization of such a detector for 4$\times$4
MIMO with 64-QAM still remains missing in open literature. To tackle this
challenge, we developed a nonlinear soft-output detector design solution, based
on which a detector for up to 4$\times$4 MIMO with 64-QAM has been designed
using 0.13$\mu$m CMOS technology. Above 75 Mbps detection throughput has been
verified based on post-layout results.
P.31 -
VLSI
Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording
Channel, H. Zhong, T. Zhang and E. Haratsch*, Rensselaer
Polytechnic Institute, *Agere Systems,
By implementing an FPGA-based
simulator, this paper investigates the semi-random construction of high-rate
regular QC-LDPC codes with low error floor for the magnetic recording channel.
Then a new QC-LDPC decoder hardware architecture is proposed. Finally, a read
channel signal processing datapath consisting of a parallel Max-Log-MAP detector
and the proposed QC-LDPC decoder is implemented in 0.13um CMOS. This design
achieves a throughput up to 1.8Gbps under 16 iterations of LDPC
decoding.
P.32 -
A
CMOS Image Sensor with combined adaptive-quantization and QTD-based on-chip
compression processor, S. Chen, A. Bermak, Y. Wang and D.
In this paper, a CMOS imager with
on-chip compression is proposed. An adaptive quantization scheme based on
boundary adaptation procedure followed by an on-line quadrant tree decomposition
processing is proposed enabling low power, robust and compact image compression
processor. The chip has been implemented using 0.35um CMOS technology.
Simulation and experimental results show compression figures corresponding to
0.6-0.8 Bit-per-Pixel, while maintaining reasonable PSNR levels and very low
power consumption.
P.33 -
Considerations
for Accurate Behavioral Modeling of High-Speed SC Sigma-Delta
Modulators, G. Suarez and M. Jimenez, University of Puerto Rico,
Mayaguez, Puerto Rico
The performance of Sigma Delta
Modulators (SDMs) is highly dependent of that of their embedded
switched-capacitor (SC) network. Therefore, detailed transient models of SC
integrators become necessary when modeling SDMs. This work presents a behavioral
transient model of a SC integrator that includes the effects of the amplifier
transconductance and output conductance relation; and the dynamic capacitive
loading effect on the settling time. Unlike traditional behavioral models where
this level of detail is usually omitted, the proposed model provides a
convenient tool to aid in the design of low-power high-speed SC Sigma-Delta
modulators. Additional nonidealities such as jitter, thermal noise and DAC
mismatch are included in a dual-band GSM/WCDMA second-order multi-bit with
individual level averaging (ILA) SDM VHDL-AMS model. Experimental data is used
to validate the model where it exhibits less than 3.0% of error in the
signal-to-noise plus distortion ratio (SNDR).
P.34 -
Width
Quantization Aware FinFET Circuit Design, J. Gu, J. Keane, S. Sapatnekar and C. Kim, University
of Minnesota, Minneapolis, MN
This paper presents a statistical
leakage estimation method for FinFET devices considering the unique width
quantization property.
P.35 -
Concurrent
Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with
the Verilog-A, T. Yamamoto, T. Suzuki and H. Asai, Shizuoka
University, Hamamatsu-shi, Japan
We present the concurrent design
method of delta-sigma modulator by using analog HDL. In our method, a few blocks
are modeled at transistor level and the other blocks are done at behavioral
level. As a result, specification of every block is derived without the enormous
costs so that the whole circuit is simulated repeatedly. We show our method is
useful and efficient for the analog circuit design by designing the first-order
delta-sigma modulator.
P.36 -
IO
Clock Network Skew & Performance Analysis: A Pentium-D Case
Study, V. Bhargava, N. Haider and N. Sarpotdar, Intel
Corporation, Santa Clara, CA
Accurate estimation of skew on IO
Clocks is extremely critical when the part is expected to operate at a fixed
frequency and any failure results in yield loss. Besides, factors such as slow
Silicon, and power saving modes makes the data-path running on I/O clocks more
critical as no timing relaxation is possible. This paper presents a systematic
skew estimation and a scientific method for performance analysis of Pentium-D IO
clock networks.
P.37 -
Nonlinear
Phase-Macromodel-Based Simulation/Design of PLLs with Superharmonically Locked
Dividers, S. Srivastava, X. Lai and J. Roychowdhury, University
of Minnesota, Minneapolis, MN
We present a novel nonlinear phase
macromodel based technique for quickly and accurately predicting superharmonic
injection locking (SHIL) in injection-locked frequency dividing (ILFD)
oscillators and PLLs. Our approach is useful for both hand analysis and
fast/accurate simulation. We derive an analytical phase slope and periodicity
based criterion for detecting SHIL from macromodel simulations and present an
insightful way of understanding SHIL phenomena using phase macromodels. We
present detailed examples of the new technique and validate our results against
full SPICE-level simulation, obtaining speedups of
150--200$\times$.
P.38 -
The
Backward-traversing Relaxation Algorithm for Circuit
Simulation, C-J.
Chen, T-N. Yang and J-D. Sun,
This paper proposes a new
relaxation-based circuit simulation algorithm that is more robust and efficient
than traditional methods such as WR and ITA. The new method simulates by
performing Depth-First Search in the signal flow graph of simulated circuits, in
which it flexibly schedules subcircuits for calculating according to converging
situations of subcircuits. A circuit simulation program based on the proposed
method has been implemented, and various circuits have been tested to justify
its performance.
P.39 -
Yield
and Cost Modeling for 3D Chip Stack Technologies, P. Mercier, S. Singh, K. Iniewski, B. Moore and P.
O'Shea, University of Alberta, Edmonton, Canada
It has been shown that stacking a set
of known good dice into a 3D chip array may be beneficial in terms of system
performance and footprint area. This paper demonstrates that, in the general
sense, it is also beneficial to arrange chips into a 3D stack from yield and
cost perspectives. It is shown that an optimal point occurs where cost is
minimized by stacking an appropriate amount of dice into a single
system.
P.40 -
On-Chip
Transient Detection Circuit for System-Level ESD Protection in CMOS
ICs, M-D.
Ker, C-C. Yen and P-C. Shih,
A new on-chip transient detection
circuit for system-level electrostatic discharge (ESD) protection is proposed in
this paper. The circuit performance to detect different positive and negative
fast electrical transients has been investigated by HSPICE simulator and
verified in silicon chip. The experimental results in a 0.13-um CMOS process
have confirmed that the proposed on-chip transient detection circuit can detect
fast electrical transients during system-level ESD zapping. The proposed
transient detection circuit can be further cooperated with power-on reset
circuit to improve the immunity of CMOS IC products against system-level ESD
stress.
P.41 -
CMOS
Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield
Improvement, D. Kim, C. Cho, J. Kim,
J-O.
Plouchart, R. Trzcinski and D.
Ahlgren, IBM Semiconductor Research and
A mixed-signal circuit’s performance
and yield dependency on process variation are investigated with numerical
circuit solution, statistical simulation, and implemented circuit measurement in
65nm partially-depleted silicon-on-insulator CMOS process. Increased relative
variation in 65nm process is examined with site-to-site and wafer-to-wafer
process variations. A current-controlled oscillator’s performance and threshold
voltages are cross-correlated up to 93.9% using simulation and RF measurement.
The yield learning process of design, simulation, measurement, and statistical
analysis is proposed.
P.42 -
In
Situ Evaluation Method for On-Chip Inductors Using Oscillator
Response, M. Motoyoshi and M. Fujishima, The University of
It is difficult to obtain the
characteristics of on-chip inductors on site since conventional evaluation
requires dedicated test devices. In this paper, in-situ evaluation of both
inductance and resistance of on-chip inductors without dedicated test devices is
proposed, where on-chip inductors are evaluated on the basis of the threshold
current for oscillation and oscillation frequency without being affected by lead
wires. The proposed method was verified by measurement, and it is found that the
error against the evaluation result using a network analyzer is less than
3%.
P.43 -
A
Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with
Robustness to Transmitter Leakage, T. Mitomo, O. Watanabe, R. Fujimoto* and S.
Kawaguchi*, Toshiba Corporation,
A quadrature demodulator (QDEMOD) for
WCDMA direct-conversion receiver using common-base input stage with on-chip
matching circuit is reported. A common-mode blocker signal, such as the
transmitter (TX) leakage signal, degrades the noise performance. We propose a
QDEMOD with a common-base input stage, that is capable of suppressing the TX
leakage signal using symmetrical inductors. The measured results show that the
NF degradation does not occur until the TX leakage signal input is larger than
-13dBm.
P.44 -
A
3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN
Applications, J. Y. Lee, K. Kim, J. Kwon,
S-C.
Lee, J. Kim, S-H. Lee, ETRI,
In this paper, we present a 3.8-5.5
GHz multi-band CMOS frequency synthesizer for WLAN and UWB applications. In the
multi-band frequency synthesizer, both new multi-mode prescaler and adaptive
multi-band LC VCO are proposed. The proposed multi-mode prescaler produces six
modes of divide-by-2/3, 4/5, 8/9, 16/17, 32/33, and 64/65. In the adaptive
multi-band LC VCO, the gate width of cross-coupled MOS array is tuned to
calibrate oscillation amplitude and alleviate 1/f flicker noise of MOS. The
multi-band frequency synthesizer represents -121 dBc/Hz at 5 MHz offset from
5.24 GHz carrier. The multi-band frequency synthesizer consumes a total current
of 26mA at 1.2 V, and is manufactured in 0.13-um CMOS process
technology.
P.45 -
Inductor-
and Transformer-based Integrated RF Oscillators: A Comparative
Study, H. Krishnaswamy and H. Hashemi,
Prior publications claim that
transformer-based resonators achieve improvements in quality factor, which
translates to better phase noise in oscillators. This paper combines rigorous
analysis with on-chip practical considerations for various types of transformers
to demonstrate the importance of resonator topology for Q-enhancement. We show
that for a fixed silicon area, transformer-based resonators do not exhibit
superior performance compared to inductor-based designs. Prototype oscillators ,
implemented at 5 GHz in a 0.18µm CMOS process, validate these
claims.
P.46 -
An
8-mW, ESD-protected, CMOS LNA for Ultra-Wideband
Applications, K. Bhatia, S. Hyvonen and E. Rosenbaum, University of
Illinois at Urbana-Champaign, Urbana, IL
A common-gate, 7.9mW, ESD-protected,
CMOS Ultra-Wideband LNA is presented. A wideband transconductance enhancement
scheme facilitates the inclusion of ESD protection at the circuit input and
reduces noise figure. Measurement results indicate that the LNA achieves a high
S21 (15dB) over the entire band, and a 4.25kV HBM ESD protection level is
projected from the measured failure current. Simulation results show low NF
(3-4dB) across the band and an input-referred 1dB CP of -11.2dBm at
5GHz.
P.47 -
X/Ku
Band CMOS LNA Design Techniques, B. Afshar and A. Niknejad, University of California,
Berkeley, CA
This paper reports two 11GHz LNA’s in
0.18µm CMOS technology. A cascade two stage LNA achieves 12dB of power gain, and
3.5dB of noise figure, while consuming 28 mA from 1.8V supply. The second LNA is
a modified cascode amplifier and it achieves 8dB of gain, and 3.1dB of noise
figure, while consuming 18 mA from the 1.8V supply. The paper also discusses
design considerations such the effects of layout on frequency tuning and
noise.
P.48 -
A
60GHz Phased Array in CMOS, S. Alalusi* and R. Brodersen,
This work comprises an array of 4
phase shifters and antennas operating at 60GHz for a beamforming system. Pass
gates form the switching core for a phase selector circuit which is replicated
to build up a vector modulator phase shifter. The final beam accuracy is better
than 2° for a 16-way system. The die area is 2.7mm×2.8mm, the buffers take 240mA
from a 1.2V supply, the pass gates take no power.
P.49 -
A
44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS
Technology, C. Lee, L-C.
Cho and S-L. Liu,
A CMOS 44GHz divide-by-4/5
dual-modulus prescaler is presented. The scaled inductive peaking technique and
the merged NOR-FF circuits are used to achieve the high-speed, low power and low
voltage operation. Fabricated in a 90nm bulk CMOS process, the prescaler with
the on-chip VCO operates from 38.7GHz to 44GHz while consuming 45mW from a 1.2V
supply. To the authors’ knowledge, this prescaler achieves the highest operation
frequency up to 44GHz in the published CMOS prescalers.
P.50 -
A
Multi-Standard Low Power 1.5-3.125Gb/s Serial Transceiver in 90nm
CMOS, D. Yokoyama-Martin, K. Krishna, J. Stonick, A. Caffee,
E. Kolet Gamble, C. Jones, J. McNeal, J. Parker, R. Segelken, J. Sonntag*, K.
Umino, J. Upton, D. Weinlader and S. Wolfer, Synopsys, Inc., *Silicon
Laboratories
A low power, small area transceiver
PHY that supports PCIeTM, SATA II, and XAUI was fabricated in TSMC's 90nm dual
gate CMOS. Each lane occupies an area of 400um x 430um. Operation also requires
a clock module of 400um x 430um. A 4-lane, wirebond testchip consumes 195mW of
power at 3.125Gb/s. The paper focuses on the analog sections of the transmit and
receive blocks.
P.51 -
FEXT
Crosstalk Cancellation for High-Speed Serial Link Design, K.-J.
Sham, M. Ahmadi, S. Bommalingaiahnapallya, G. Talbot* and R. Harjani,
We have proposed and verified an
efficient architecture for a high-speed I/O transceiver design that implements
far-end crosstalk (FEXT) cancellation. In this design, TX pre-emphasis, used
traditionally to reduce ISI, is combined with FEXT cancellation at the
transmitter to remove crosstalk-induced jitter and interference. The
architecture has been verified via simulation models based on channel
measurement. A prototype implementation of a 12.8Gbps source-synchronous serial
link transmitter has been developed in 0.18um CMOS. The proposed design consists
of three 12.8Gbps data lines that uses a half-rate PLL clock of 6.4GHz. The chip
includes a PRBS generator to simplify multi-lane testing. Simulation results
show that, even with a 2X reduction in line separation, FEXT cancellation can
successfully reduce jitter by 51.2% UI and widen the eye by 14.5%. The 2.5x1.5
mm^2 core consumes 630mW per lane at 12.8Gbps with a 1.8V
supply.
P.52 -
A
Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd
Generation Serial-ATA, J. Shin, I. Seo, J.Y. Kim, S.-H. Yang, C. Kim, J. Pak,
H. Kim, M. Kwak and G.B. Hong, Samsung Electronics, Kiheung,
Korea
A low-jitter added 3GHz
spread-spectrum clock generator with seamless phase selection and a fast
automatic frequency calibration (AFC) was implemented in 90nm CMOS process. The
proposed SSCG takes full advantage of multi-phase switching with increased
sigma-delta operation speed. A fast frequency calibration is done with direct
counting VCO clock. The measurements show that only 2.7ps peak-to-peak jitter is
added by spread-spectrum clocking and 400ns of unit frequency comparison time is
achieved in AFC process.
P.53 -
A
5Gb/s Transmitter with Reflection Cancellation for Backplane
Transceivers, R. Yuen, M. van Ierssel, A. Sheikholeslami,
W.
We present a 5Gb/s transmitter that
cancels the reflected signals from any impedance discontinuity located at up to
64UI away from the transmitter and spread over 8UI interval. Measured results
from our 0.11um CMOS design reveal a 150mV eye-opening, from a nearly closed
eye, when reflection cancellation is activated. The design consumes 510uA for
the PLL operation, 60mA for data generation, and 50mA for data transmission, all
from a 1.2V supply.
P.54 -
Phase
Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock
Generator, A. Tan
and G-Y. Wei,
Device mismatch and systematic
imbalances in the physical design can cause static phase mismatch in a PLL/DLL
based multi-phase clock generator and degrade performance. This problem gets
worse in deep sub-micron technologies. Interleaved transceiver architectures
require precise clocking to maximize data rate and minimize bit errors. In this
paper, a static phase mismatch compensation scheme for multiple sampling clocks
is proposed and tested in an adaptive-bandwidth mixing PLL/DLL based multi-phase
clock generator. The proposed charge pump compensator and power efficient
phase-averaging network together reduce the static phase mismatch standard
deviation by 37% when operating in DLL mode. A simple and robust duty-cycle
correction circuit exhibits a small residual error of 0.65% across a wide range
(36% to 49%) of input clock duty-cycle values.