10:05

02-1

Process Variability at the 65nm Node and Beyond (INVITED), Sani Nassif, IBM Austin Research Laboratory, Austin, TX

The impact of manufacturing-induced variations has been well established as a first order impediment to modern integrated circuit design. Numerous research efforts are underway to understand and characterize variability, to predict its impact on circuit behavior, and to develop layout and circuit design techniques to reduce the impact of variability. Simultaneously, except for the most advanced high performance designs, the increasing cost of migrating to sub-65nm technology nodes is slowing down adoption, allowing current efforts to catch up and effectively help current design trends. The future of CMOS technology scaling, however, is such that the impact of variability on design it going to change in character, not just magnitude. Phenomena that currently effect the parametric performance of circuits are expected to reach magnitudes which will impact the correctness aspects of circuits. This paper examines the sources and current trends of process variability, and shows concrete examples of the new challenges we are facing when the magnitude of variability is such that its impact is indistinguishable from catastrophic faults.

10:55

02-2

Mismatch Analysis and Statistical Design at 65 nm and Below (INVITED), Larry Pileggi, Gökçe Keskin, Xin Li, Ken Mai and Jon Proesel, Carnegie Mellon University, Pittsburgh, PA

Transistor sizing to control random mismatch is investigated. Input offset voltage of 65nm CMOS SRAM sense amplifiers are measured to analyze NMOS and PMOS threshold voltage variation effects and compare them with statistical models and Pelgrom model predictions. Statistical models for post-manufacturing are postulated and shown for sub-65nm technologies.

11:20

02-3

Statistical Prediction of Circuit Aging under Process Variations, Wenping Wang, Vijay Reddy, Bo Yang, Varsha Balakrishnan, Srikanth Krishnan and Yu Cao, Arizona State University, Tempe, AZ and Texas Insturments, Dallas, TX

Accurate prediction of circuit aging and its variability is essential to eliable design and analysis. Such a capability further helps reduce the load in statistical reliability test. Based on compact models of transistor egradation and circuit performance, we develop analytical solutions that fficiently predict the statistics of both circuit timing and the leakage under temporal stress and process variations. These solutions prove that circuit aging and its variance can be fully predicted from the characteristics of transistor degradation and circuit performance sensitivity to aged parameters, independent on the type and the amount of process variations. Specific results include: (1) under variations, the standard deviation of circuit speed declines with the stress time, following a power law of 1/6; and (2) the logarithmic mean and the standard deviation of leakage current decrease with the stress time as t^1/6. The results are systematically validated by simulation and measurement data from an industrial 65nm technology, enhancing the predictability and efficiency of statistical reliability analysis.

10:05

03-1

A Fully-Integrated 0.18µm CMOS DC-DC Step-Down Converter, Using a Bondwire Spiral Inductor, Mike Wens and Michiel Steyaert, Katholieck University, Leuven, Belgium

A fully-integrated DC-DC step-down converter in a 0.18µm 1.8V CMOS technology is realized, with a bondwire spiral inductor and integrated MOS and MIM capacitors. The converter is designed to generate an output voltage of 1.8V out of a 3.6V power supply. The maximum power conversion efficiency is 65%.

10:30

03-2

A 90-240MHz Hysteretic Controlled DC-DC Buck Converter with Digital PLL Frequency Locking, Pengfei Li, Deepak Bhatia, Xue Lin and Rizwan Bashirullah, University of Florida, Gainesville, FL

This paper reports a digital phase locked loop (DPLL) frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed technique achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or output voltage conversion range. The DPLL is programmable over a wide range of parameters and can be locked to a reference clock to ensure the converter switching frequency falls outside power supply resonance bands. We demonstrate a 90-240MHz single phase converter with fast hysteretic control and output conversion range of 33%-80%. The converter achieves an efficiency of 80% at 180MHz, a load response of 40ns for a 120mA current step and a peak-to-peak ripple less than 25mV. The circuit was implemented in 130nm digital CMOS process.

10:55

03-3

Fast Transient Technique (FTT) in Buck Current-Mode DC-DC Converters for Low-Voltage SoC Systems, Chia-Hsiang Lin*, Hong-Wei Huang**, Ke-Horng Chen**, National Chiao Tung University,Taiwan, ROC, **Rich Tek Technology, Taiwan, ROC

This paper proposes a fast transient technique (FTT) to achieve excellent transient response of current-mode buck DC-DC converters. The proposed technique combines a non-linear control and a linear control mechanism to achieve fast transient response time, low output ripples, and stable transient operation at the same time. The test chip was fabricated in UMC 0.18-um process. Experimental results show that the transient undershoot/overshoot voltage and the recovery time are not exceed 48mV and 10us, respectively.

11:20

03-4

A Process Variation Compensation Scheme Using Cell-Based Forward Body-biasing Circuits Usable for 1.2V Design, Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki*, Shuuji Matsumoto*, Yoshinori Watanabe* and Mototsugu Hamada, Toshiba Corporation, Kawasaki, Japan, *Toshiba Microelectronics Corp., Kawasaki, Japan

A cell-based forward body-biasing technique to suppress die-to-die variation is proposed.  Latch-up free operation is guaranteed by embedded current source cells and limiter cells even when supply voltage is 1.2V.  By applying this technique to a media-processor, the worst-case delay is reduced by 20% without sacrificing the maximum leakage spec.

11:45

03-5

Built-in Resistance Compensation (BRC) Technique for Fast Charging Li-Ion Battery Charger, Chia-Hsiang Lin, Hong-Wei Huang*, and Ke-Horng Chen*, National Chiao Tung University, Taiwan, ROC, *National Taiwan University, Taiwan, ROC

This paper presents a BRC technique to speed up the charging time of the Li-Ion battery. Due to the physical properties of the battery cell, the charger circuit charges the cell with three stages, which are trickle current (TC), constant current (CC), and constant voltage (CV) stages. Due to the internal parasitic resistance of the Li-Ion battery pack system, the charger circuit switches from the CC stage to the CV stage without fully charging the cell to the rated voltage value. At the CV stage, the cell is needed to be charged by a degrading current since the over-charging current may damage the Li-Ion cell. The longer the cell stays at the CV stage, the longer the charging time is due to the degrading current. The BRC technique can dynamically estimate the internal resistance of the battery pack system to extend the period of the CC stage. The test chip was fabricated in TSMC 0.35 um process. Experimental results show the period of the CC stage can extended to about 40% that of the original design. The charging time can be effectively reduced.

10:05

04-1

A Voltage Drop Aware Crosstalk Measurement with Multi-Aggressors in 65nm Process, Genichi Tanaka, Kan Takeuchi, Minoru Ito* and Hiroaki Matsushita, Renesas Technology Corp., Hyogo, Japan, *Hitachi Information & Communications Engineering, Tokyo, Japan

An efficient crosstalk delay degradation measurement method with a 65nm process is proposed.  The dependence of crosstalk delay on 1) aggressor noise injection timing, 2) aggressor location and direction, and 3) voltage drop has been measured.  Simulation and measurement results are precisely matched with much less than 10% errors.

10:30

04-2

Measurements of the Silicon Die Characteristics of Packaged Drivers for High-Speed I/O (INVITED), Gerry Talbot and Edoardo Prete, Advanced Micro Devices

As the data rates of high-speed I/O interfaces increase beyond 5Gb/s it is difficult to separate out the effects of silicon performance from the interaction of package and test fixture.  This work describes a method to measure a packaged device and to separately extract silicon characteristics and package S-parameters.

11:20

04-3

Inductor-Based ESD Protection under CDM-like ESD Stress Conditions for RF Applications, Steven Thijs, Mototsugu Okushima, Borremans Jonathan, Philippe Jansen, Dimitri Linten, Mirko Scholz, Piet Wambacq and Guido Groeseneken, IMEC, Leuven, Belgium

Charged Device Model (CDM) ElectroStatic Discharge (ESD) stress is a major concern for inductor-based ESD protection strategies for RF circuits processed in advanced nano-CMOS technologies. The CDM robustness of such protection methodology is investigated in this paper based on Very-Fast Transmission Line Pulse (VFTLP) measurements. Its applicability is discussed for future technologies and RF applications.

11:45

04-4

Non-Destructive IC Defect Localization Using Optical Beam-Based Imaging (INVITED), Edward Cole Jr., Sandia National Laboratories, Albuquerque, NM

Optical beam failure analysis methods provide unique capabilities to identify and localize defect types that would be difficult or impossible by other methods. This review talk describes the physics of signal generation and several examples demonstrating the strengths of each technique as well as future directions for improvement.

10:05

05-1

Emerging Application Opportunities for SiGe Technology (INVITED), John Cressler, Georgia Institute of Technology, Atlanta, GA

Bandgap-engineered SiGe HBTs are fully Si-manufacturing compatible, and can be fabricated in a BiCMOS platform on 200 mm wafers at high yield. SiGe HBTs are capable of extremely high frequency operation, exhibit very low broadband and 1/f noise, and high transconductance per unit area, all at very modest lithographic nodes, making them near-ideal devices for high-speed, mixed-signal circuits. In this work we discuss new technology trends, ultimate performance limits, and emerging application opportunities in SiGe technology.

10:55

05-2

A 0.8GHz-10.6GHz SDR Low-Noise Amplifier in 0.13-um CMOS, Shuzuo Lou and Howard Luong, Hong Kong University of Science and Technology, Hong Kong, China

A low-noise amplifier (LNA) is designed for SDR. Noise-cancellation common-gate stage is combined with capacitive coupling for impedance matching, with inductive peaking networks to reject loading resistors noise, and with IM2 injection for linearization. Under 1.5 V in 0.8-10.6GHz, the 0.13um CMOS LNA measures 16-dB gain, 3.4-5.6dB NF, 1.6-dBm IIP₃.

11:20

05-3

A 1.3-6 GHz Triple-Mode CMOS VCO Using Coupled Inductors, Zahra Safarian and Hossein Hashemi, University of Southern California, Los Angeles, CA

An integrated VCO with ultra-wide tuning range is designed and fabricated in 0.13um CMOS technology.  The triple-mode VCO uses 6th-order resonator based on three coupled inductors with compact common-centric layout, banks of switched varactors, and continuously-tuned varactors to cover the measured 1.28-6.06GHz.

1:35

06-1

A SOC/SOP Co-design Approach for mmW CMOS in QFN Technology (INVITED), Joy Laskar, Stephane Pinel, Padmanava Sen, Bevin Perumana, Debasis Dawn, David Yeh and Francesco Barale, Georgia Institute of Technology, Atlanta, GA

The past few years have witnessed the emergence of CMOS based circuits operating at millimeter wavefrequencies. The co-design of fully integrated mmW CMOS single chip digital radios with low cost QFN packages operating from 30 to 100GHz offers the promise for high volume manufacturing which paves the way for a new millimeter-wave industry. As standardization efforts catalyzed the interest and investment of industry and agencies, one can be assured of ubiquitous millimeter-wave technology in the consumer electronic market place in the fairly near future.

2:25

06-2

Chip to Carrier C4 Technology Challenges with Pb-free Solders (INVITED), Eric Perfecto, Brian Sundlof, Kamalesh Srivastava and Minhua Lu*, IBM Systems & Technology Group, Hopewell Junction, NY, *IBM Watson Research

The simultaneous requirements of increased power and current, increased I/O counts and larger chips, and weak BEOL structure, demand careful selection of under bump metallurgy, chip solder, laminate, laminate surface finish and underfill. Chip-Package interaction and electromigration challenges with Pb-free C4 bumping will be discussed.

2:50

06-3

A Study on Process-compatibility in CMOS-first MEMS-last Integration, Kazuhiro Takahashi, Makoto Mita, Hiroyuki Fujita, Kazuhiro Suzuki*, Hideyuki Funaki*, Kazuhiko Itaya* and Hiroshi Toshiyoshi, University of Tokyo, Tokyo, Japan, *Toshiba Corp., Kanagawa, Japan

We report monolithic integration of MEMS actuators and high-voltage driver circuits into an SOI chip. We investigated the process compatibility between IC and MEMS.  Studies are made on (1) fabrication of the MEMS-circuit electrical interconnection and (2) the effect of dry-etching plasma on the circuit characteristics in MEMS process.

1:35

07-1

A 101-dB SNR Hybrid Delta-Sigma Audio ADC using Post Integration Time Control, Moo-Yeol Choi, Sung-No Lee, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim and Hae-Seung Lee*, Samsung Electronics, Yongin, Korea, *Massachusetts Institute of Technology, Cambridge, MA

A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65nm CMOS process, dissipates 15mW and occupies an active die area of 0.28mm2. A post integration time control (PITC) technique is proposed for calibration of the RC time constant variation of the continuous-time integrator. In addition, a jitter insensitive pulse generator (JIPG) circuit overcomes the degradation of SNR due to the feedback DAC clock jitter. The measured SNR and DR are 101dB and THD is -94dB.

2:00

07-2

An 8.1 mW, 82 dB Delta-Sigma ADC with 1.9 MHz BW and -98 dB THD, Kyehyung Lee, Matthew R. Miller* and Gabor C. Temes, Oregon State University, Corvallis, OR, *Freescale Semiconductors, Lake Zurich, IL

A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. It provides 81 dB SNDR, 82 dB dynamic range, and -98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 V power supply (analog power 4.4 mW, digital power 3.7 mW). Its figure-of-merit is among the best reported for wideband ADCs.

2:25

07-3

A 2.5MHz BW and 78dB SNDR Delta-Sigma Modulator Using Dynamically Biased Amplifiers, Yan Wang, KyeHyung Lee and Gabor Temes, Oregon State University, Corvallis, OR

A new dynamically-biased scheme is proposed to implement a 13-bit delta-sigma modulator with a 2.5 MHz signal bandwidth. It uses the low-distortion architecture, and hence the opamp linearity requirements are greatly relaxed. Its noise-coupled and time-interleaved structure further decreases the power consumption. The prototype chip was fabricated in a 0.18um CMOS technology. Experimental results show that 78dB SNDR is achieved when it is clocked at 60MHz sampling rate. With 1.6V power supply, the power dissipation is 19.2 mW

2:50

07-4

74dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35dB Opamp Gain, Nima Maghari, Sunwoo Kwon and Un-Ku Moon, Oregon State University, Corvallis, OR

In this paper a new multi-loop delta-sigma modulator is presented. This multi-loop modulator is insensitive to low gain opamps while maintaining the stability advantage. As a proof of concept, a prototype was implemented to show the functionality of this structure. Measurement results shows that with open-loop opamp gain of only 35dB, this prototype achieves over 74dB SNDR at oversampling ratio of 16. The sampling frequency is 20MHz and the total power dissipation is 3.2mW from a 1.2V power supply.

3:30

07-5

A/D Converter Trends: Power Dissipation, Scaling and Digitally Assisted Architectures (INVITED), Boris Murmann, Stanford University, Stanford, CA

This paper summarizes recent trends in the area of low-power A/D conversion. Survey data collected over the past eleven years indicates that the power efficiency of ADCs has improved on average by a factor of two every two years. A closer inspection on the impact of technology scaling is presented to explain the observed trend in the context of shrinking supply voltages and increasing device speed. Finally, a discussion on minimalistic and digitally assisted design approaches is used to sketch a route toward further improvements in ADC power efficiency and performance.

4:20

07-6

A 16b 10MS/s Digitally Self-Calibrated ADC with Time Constant Control, Tae-Hwan Oh, Ho-Young Lee, Ju-Hwa Kim, Ho-Jin Park, Kyoung-Ho Moon, Jae-Whui Kim and Hae-Seung Lee*, Samsung Electronics Co., Ltd., Yongin-City, Korea, *Massachusetts Institute of Technology, Cambridge, MA

Time constant control incorporating on-chip digital self-calibration performs two-step calibration of pipeline ADC stage errors and reduces power consumption at the same time. Using the proposed technique, the current of the amplifier is reduced by 93%. The prototype 16b 10MS/s ADC implemented in an active die area of 1.32mm² consumes 79.2mW. The measured DNL, INL, and SNDR are ±0.65 LSB, ±5.76LSB, and 75.4dB, respectively.

4:45

07-7

A 15b Power-Efficient Pipeline A/D Converter Using Non-Slewing Closed-Loop Amplifiers, Shoji Kawahito, Kazutaka Honda, Zheng Liu, Keita Yasutomi and Shinya Itoh, Shizuoka University

A 15b power-efficient pipeline A/D converter using capacitance-coupling non-slewing amplifiers is presented.  A modified 1.5b/stage transfer curve combined with the non-slewing amplifier is useful for the error corrections of incomplete settling error. A prototype ADC fabricated in 0.25um process consumes 123mW at 30MSample/s and 2.5V power supply. The SNDR and the SFDR at 30MS/s are 75.0 dB and 86.5 dB, respectively with the incomplete settling error corrections.

1:35

08-1

An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization, John Keane, Shrinivas Venkatraman, Paulo Butzen and Chris Kim

We propose an array-based circuit for characterizing gate dielectric breakdown.  Such a design is beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution.  Measurement results are presented from a 32x32 test array implemented in a 130nm process.

2:00

08-2

A High Sensitivity Process Variation Sensor Utilizing Sub-threshold Operation, Mesut Meterelliyoz, Peilin Song*, Franco Stellari*, Jaydeep P. Kulkarni and Kaushik Roy, Purdue University, West Lafayette, IN, *IBM T.J. Watson Research Center, Yorktown Heights, NY

We propose a novel low-power, bias-free, high-sensitivity process variation sensor for monitoring random variations in threshold voltage. Our design utilizes the exponential current-voltage relationship of sub-threshold operation for improved sensitivity. Measurement results on 28 dies fabricated in 65nm bulk CMOS technology demonstrate the effectiveness of the proposed sensor.

2:25

08-3

Measurement and Analysis of Variability in 45nm Strained-Si CMOS Technology, Liang-Teck Pang and Borivoje Nikolic, University of California, Berkeley, CA

A test-chip in a low-power 45nm technology, featuring uniaxial strained Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured and analyzed. Delay is characterized using an array of ring-oscillators and transistor leakage current is measured with an on-chip ADC. Results show that systematic variations are small and layout-induced variation is dominated by strain effects.

2:50

08-4

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator, Bishnu Prasad Das, Bharadwaj Amrutur, H.S. Jamadagni, N.V. Arvind and V. Visvanathan

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

3:15

08-5

Expected Vectorless Teacher-Student Swap (TSS) Test Method with Dual Power Supply Voltages for 0.3V Homogeneous Multi-core LSI’s, Taro Niiyama, Koichi Ishida, Makoto Takamiya and Takayasu Sakurai, University of Tokyo, Tokyo, Japan

A Teacher-Student Swap (TSS) test method with the dual supply voltage (VDD) for the ultra low VDD homogeneous multi-core LSI’s is proposed and the test chips are fabricated in 90 nm CMOS. In this method, two same cores with different power supply voltages test each other by comparing their outputs, which eliminates the need for the expected vector. When VDD is less than 0.3V, the die-to-die power reduction by the dual VDD in the 5 chips was from 18% to 48%. In order to manage the large die-to-die variations at low VDD, the fine grain dual VDD with TSS test method is a promising approach without increasing the test cost.

1:35

09-1

MIMO Techniques for High Data Rate Radio Communications (INVITED), Yorgos Palaskas, Ashoke Ravi and Stefano Pellerano, Intel Corporation, Hillsboro, OR

This paper presents a simplified overview of general MIMO theory, and a specific 2x2 MIMO 5GHz WLAN transceiver in 90nm CMOS. MIMO crosstalk is shown to have a detrimental effect on MIMO performance and crosstalk mitigation techniques are proposed. The paper concludes with upcoming MIMO-related applications, e.g. 60GHz phased-array communications.

2:25

09-2

Wireless Interconnection within a Hybrid Engine Controller Board, Swaminathan Sankaran, Kyujin Oh, Hsinta Wu and Kenneth O, Univerisyt of Florida

Wireless interconnection within a hybrid engine controller board has been demonstrated by demodulating an AM signal transmitted with on-chip antenna using a receiver located in the board. The receiver centered between 14-16GHz uses a Schottky diode detector and does not require a crystal frequency reference. The receiver occupies ~1.5mm2, consumes ~60mW and can support upto 400 Mbps.

M-01

A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS, Jonathan Proesel and Lawrence Pileggi, Carnegie Mellon University, Pittsburgh, PA

An inverter-based 5-bit flash ADC in 90nm digital CMOS is presented. Comparators are formed using digital inverters and resistors. The ADC achieves low freq. ENOB of 4.45 bits without calibration. Voltage scaling is demonstrated by 60MS/s to 600MS/s operation from 0.6V to 1V. A FoM of 0.49pJ/conv is obtained.

M-02

A 10~15b 60MS/s Floating-Point ADC with Digital Gain and Offset Calibration, Yun-Shiang Shu, Moon-Jung Kyung, Wei-Ming Lee, Bang-Sup Song and Bedabrata Pain*, University of California, La Jolla, CA, *Jet Propulsion Laboratory, Pasadena, CA

A variable-gain amplifier with pseudo-random noise signal-dependent dithering and chopping is proposed. It allows the ADC gain and offset errors to be digitally-calibrated in background. A 10~15b 60MS/s floating-point ADC with variable gains from 1 to 32 enhance the INL from 24 to 0.9LSB of 15b after calibration.

M-03

Digital Correction of Dynamic Track-and-Hold Errors Providing SFDR > 83 dB up to fin = 470 MHz, Parastoo Nikaeen and Boris Murmann, Stanford University, Stanford, CA

A digital technique for the compensation of dynamic nonlinearities at the front-end of high-speed, high-resolution ADCs is presented. The complexity of the digital post-processing scheme is minimized using judicious modeling of the relevant nonidealities. Applying the method to a 14-bit, 155-MS/s ADC provides > 83 dB SFDR up to fin = 470 MHz. The post-processing block is estimated to consume 52 mW and occupy 0.54 mm2 in 90-nm CMOS.

M-04

A 65nm CMOS 1.2V 12b 30MS/s ADC with Capacitive Reference Scaling, Kang-Jin Lee, Kyoung-Jun Moon, Kwang-Sung Ma, Kyoung-Ho Moon and Jae-Whui Kim, Samsung Electronics Co., Ltd., Gyeonggi-Do, Korea

A 1.2V 12b 30MS/s pipelined ADC, implemented in a 65nm standard CMOS technology, achieves an SNDR of 65.1dB with a rail-to-rail 4.7MHz input.  A capacitive reference scaling technique is proposed to alleviate the high gain requirement of the opamp and a wide input range of 2.4Vp-p differential for low voltage operation in the nanometer domain.  The prototype ADC dissipates 18mW and occupies an active die area of 0.34mm².  The measured DNL and INL are ±0.44LSB and ±1.33LSB, respectively.

M-05

A Continuous-time Input Pipeline ADC, David Gubbins, Bumha Lee*, Pavan Kumar Hanumolu and Un-Ku Moon, Oregon State University, Corvallis, OR, *National Semiconductor, Santa Clara, CA

A new pipeline ADC architecture that employs a continuous-time first stage followed by a conventional switched capacitor pipeline ADC is presented. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture and leads to a low area, low power solution with excellent distortion performance. Measured results obtained from a proof of concept test chip fabricated in a 0.18um CMOS process validate the effectiveness of proposed techniques.

M-06

A 0.8 V Asynchronous ADC for Energy Constrained Sensing Applications, Michael Trakimas and Sameer Sonkusale, Tufts University, Medford, MA

This paper discusses the design of an asynchronous analog-to-digital converter targeted for low-power sensing applications. The asynchronous sampling scheme will save power because it only samples the input signal when it is changing. The idea of using an adaptive resolution to increase the maximum input frequency of the ADC is introduced. A prototype chip has been fabricated in a 0.18 µm CMOS process. Initial measurement results are presented.

M-07

Modeling, Design and Optimization of Hybrid Electromagnetic and Piezoelectric MEMS Energy Scavengers, Xiaochun Wu, Alireza Khaligh and Yang Xu, Illinois Institute of Technology, Chicago, IL

A hybrid energy scavenging technique through electromagnetic and piezoelectric mechanisms is introduced for MEMS structures. A unified energy conversion model is proposed to capture the relation of the recoverable energy and the input vibration frequency and amplitude. Design and optimization of a hybrid MEMS energy scavenger design example are shown as illustration.

M-08

Amorphous Silicon Logic Circuits on Flexible Substrates, Rahul Shringarpure, Lawrence Clark, Sameer Venugopal, David Allee and Shrinivas Uppili, Arizona State University, Tucson, AZ

This paper describes the design of amorphous silicon (a-Si:H) logic circuits using static and dynamic programmable logic arrays (PLA’s) as the baseline examples. The PLA’s are designed with n-channel a-Si:H thin film transistors (TFT’s) manufactured in a low temperature (180ºC) process for flexible substrates. Measured and simulated results demonstrate that dynamic circuits are the best design approach, from both a power and delay viewpoint, for a-Si:H flexible logic circuits.

M-09

Frequency Tunable Silicon Carbide Resonators for MEMS Above IC, Frederic Nabki, Tomas A. Dusatko and Mourad N. El-Gamal, McGill University, Montreal, Canada

Micro-electromechanical beam resonators and arrays are fabricated using a custom low-temperature CMOS-compatible silicon carbide micro-fabrication process. A special feature of this process is the integration of heaters directly onto the MEMS devices, thus enabling resonant frequency tuning, with constant insertion loss and considerable extension of the tuning range.

M-10

MEMS Wafer-Level Vacuum Packaging with Transverse Interconnects for CMOS Integration, Dominique Lemoine, Paul-Vahé Cicek, Frederic Nabki and Mourad El-Gamal, McGill University, Montreal, Canada

A novel vacuum wafer-level packaging technology for micro-electromechanical systems (MEMS) is presented. It supports monolithic integration with electronics, and it is suitable for different MEMS processes. Bulk-etched transverse feedthroughs are used to connect with the encapsulated systems. Silicon carbide is successfully used for membrane stress cancellation and improved hermeticity.

M-11

Variation-Tolerant Spin-Torque Transfer (STT) MRAM Array for Yield Enhancement, Jing Li, Haixin Liu, Sayeef Salahuddin and Kaushik Roy, Purdue University, West Lafayette, IN

Spin-Torque Transfer MRAM is a promising candidate for future universal memory, but its yield is severely affected by process variations. In this paper, we analyze the failure mechanisms in STT MRAM and develop an optimization methodology for robust 1T1M cell design based on comprehensive physics-based model (Non-Equilibrium Green's Function (NEGF)). We further propose a variation-tolerant circuit design, leading to considerably improved yield. Simulation results show that robustness is improved by 36% with 9% area overhead.

M-12

Pure Logic CMOS Based Embedded Non-Volatile Random Access Memory for Low Power RFID Application, Liyang Pan, Xian Luo, Yaru Yan, Jirong Ma, Dong Wu and Jun Xu, Tsinghua University, Beijing, China

Based on a novel two-dimension array architecture, a 1.8V 0.44mm2 1Kbits embedded Non-Volatile Random Access Memory (NVRAM) IP is developed with 0.18um standard CMOS process for RFID application. Several high voltage solutions are proposed to improve the reliability and safety. Furthermore, the power consumption for read and write operations are controlled under 312uA and 88uA respectively.

M-13

A High-speed, Low-power 3D-SRAM Architecture, H. Henry Nho, Mark Horowitz and S. Simon Wong, Stanford University, Stanford, CA

This paper presents a novel 3D-SRAM architecture that significantly reduces the bit-line capacitance, achieves 3.4 times reduction in active power consumption and 1.8 times reduction in access time. A proof-of-concept 32Kb sub-array emulating the critical path of the 3D-SRAM has demonstrated about 5 times improvement in power-delay over conventional 2D-SRAM.

M-14

Early Prediction of Product Performance and Yield Via Technology Benchmark, Choongyeun Cho, Daeik Kim, Jonghae Kim*, Daihyun Lim** and Sangyeun Cho***, IBM Semiconductor R&D Center, Hopewell Junction, NY, *Qualcomm Inc., San Diego, CA, **MIT MTL, Cambridge, MA, ***University of Pittsburgh, Pittsburgh, PA

This paper presents a practical method to estimate IC product performance and parametric yield from a well chosen set of electrical measurements intended for technology monitoring at an early stage of manufacturing.  We demonstrate that the mmWave circuit and logic performances in 65nm technology are predicted within 5% RMS error.

M-15

A FPGA Vernier Digital-to-Time Converter with 3.56ps Resolution and -0.23~+0.2LSB Inaccuracy, Poki Chen, Juan-Shan Lai and Po-Yu Chen, National Taiwan University of Science and Technology, Taiwan, ROC

A simple but powerful digital-to-time converter realizable with FPGA chips is proposed. Based on vernier principle, the effective resolution is made equivalent to the period difference of two PLL outputs and is achieved as fine as 3.56ps. The measured INL is -0.23~0.2LSB only. The operation range is verified to be 33.4 minutes. Only two embedded PLLs and some standard logic cells are required for circuit realization. The design effort and chip cost are lowered substantially.

M-16

RASP 2.8: A New Generation of Floating-gate based Field Programmable Analog Array, Arindam Basu, Christopher M. Twigg*, Stephen Brink, Paul Hasler, Csaba Petre, Shubha Ramakrishnan, Scott Koziol and Craig Schlottman, Georgia Institute of Technology, Atlanta, GA, *Binghamton University, Binghamton, NY

The RASP 2.8 is a reconfigurable analog system with thirty-two computational analog blocks (CABs). Each CAB has a wide variety of sub-circuits. The programmable interconnects and CAB elements are implemented using floating-gate transistors. This system exhibits 9 bits of programming accuracy over 100fA to 10uA.  Programming time is 5ms/bias and 100us/row of switches. Isolation between ON and OFF switches is improved by indirect programming and source-selection methods. Several complex system examples are presented.

M-17

Modeling of Triple-Well Isolation and the Loading Effects On Circuits up to 50 GHz, Piljae Park and C. Patrick Yue, University of California, Santa Barbara, CA

This paper presents the noise isolation characteristics and substrate loading effects of NMOS devices in triple-well. Our study reveals that using large well bias resistors are beneficial to circuit performance in both saturation and triode mode. However, small bias resistances are advantageous for better substrate noise isolation.

M-18

A General Weak Nonlinearity Model for LNAs, Wei Cheng, Anne Johan Annema, Jeroen Croon*, Dick Klaassen* and Bram Nauta, University of Twente, Enschede, The Netherlands, *NXP-TSMC Research Center, Eindhoven, The Netherlands

This paper presents a general weak nonlinearity model for various low noise amplifier topologies in both narrowband and wideband applications. Represented by compact closed-form expressions our model can be easily utilized by both circuit designers and LNA design automation algorithms without involving any complex nonlinearity analysis.

M-19

Modeling and Synthesis of Wide-Band Switched-Resonators for VCOs, Bodhisatwa Sadhu, Umaikhe Omole and Ramesh Harjani, University of Minnesota, Minneaoplis, MN

A two-level switched resonator model for synthesizing wide-tuning range LC VCOs is described. Based on the model, a synthesis framework is developed. An example VCO designed in 0.18µm CMOS using this framework provides a 3.35 to 8.34 GHz frequency range with -107 to -119 dBc/Hz phase noise at 1MHz offset.

M-20

Faster Statistical Cell Characterization using Adjoint Sensitivity Analysis, Ben Gu, Kiran Gullapalli, Yun Zhang and Savithri Sundareswaran, Freescale Semiconductor, Austin, TX

In this work, we propose an improved transient sensitivity analysis to accelerate statistical characterization of standard cells. By exploiting the sparsity of dependence of devices on local statistical parameters and ignoring time points with insignificant contributions we obtain a method that is dramatically the conventional approach.

M-21

An ESD-Protected 5-GHz Differential Low-Noise Amplifier in a 130-nm CMOS Process, Yuan-Wen Hsiao and Ming-Dou Ker, National Chiao-Tung University, Taiwan, ROC

A novel ESD protection design for differential I/O pads is proposed and applied to a 5-GHz differential LNA in a 130-nm CMOS process. In the proposed ESD protection design, an ESD bus and a local ESD clamp device are added between the differential input pads to quickly bypass ESD current, especially under the pin-to-pin ESD-stress condition. With 10.3-mW power consumption, the differential LNA with the proposed ESD protection design has 3-kV HBM ESD robustness, and exhibits 18-dB power gain and 2.62-dB noise figure at 5-GHz.

M-22

A 65nm 3.4Gbps HDMI TX PHY with Supply-regulated Dual-tuning PLL and Blending Multiplexer, Jongshin Shin, Jaehyun Park, Bongjin Kim, Jongjae Ryu, Chiwon Kim, JiYoung Kim, Seung-Hee Yang, Hyungoo Kim and Jaewhui Kim, Samsung Electronics, Yongin-Si, Korea

A 65nm 3.4Gbps HDMI TX PHY was designed with supply-regulated dual-tuning PLL and blending multiplexer. It uses a new dual-tuning scheme for small capacitor and low-jitter while keeping the supply regulation capability. A fractional-N operation was implemented with a blending multiplexer which enables seamless switching of high-speed multiphase clock.

M-23

A Scalable Digitalized Buffer for Gigabit I/O, Hung Wen Lu, Chau Chin Su* and Chien-Nan Liu, National Central University, Taiwan, ROC, *National Chiao-Tung University, Taiwan, ROC

A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18µm CMOS process, the I/O occupies an area of 0.014mm2 and operates from 4Gbps@1.9V to 1.5Gbps@1.1V.

M-24

Broadband Transimpedance Amplifier in 0.35-um SiGe BiCMOS Technology for 10-Gb/s Optical Receiver Analog Front-End Application, Ji-Chen Huang, Yu-Sheng Lai and Klaus Yune-Jane Hsu, National Tsing Hua University, Taiwan, ROC

This paper presents the implementation of a fully integrated optical receiver analog front-end, which uses a capacitance immunization technology to enhance gain-bandwidth performance. In addition, the area-efficient receiver provides an excellent gain-bandwidth product per DC power figure-of-merit of 10542.4 GHz-ohm/mW under a 1.1 pF input capacitance and a 3-V supply.

M-25

A Multifunction Transceiver RFIC for 802.11abg WLAN and DVB-H Applications, Yin Shi, Fa Foster Dai*, Jun Yan, Xueqing Hu, Hua Xu, Ming Gu, Xuelian Zhang, Qiming Xu, Bei Chen, Fangxiong Chen, Peng Yu, Heping Ma, Fang Yuan and Richard Jaeger*, CAS Semiconductor Integration Technology Research Center, Suzhou, China, *Auburn University, Auburn, AL

We present a multifunction wireless transceiver RFIC for WLAN and DVB-H applications. The RFIC includes a super-heterodyne transceiver for IEEE 802.11a/b/g WLAN applications and a zero-IF receiver for DVB-H application. The WLAN and DVB-H transceiver share the down-conversion mixers, the baseband VGAs, filters, and the PLL synthesizer, resulting in a small silicon area of 20mm2. Using a 3.3V supply, the power consumption of the WLAN transceiver and the DVB-H receiver are 462mW and 396mW, respectively.

M-26

A Fully Integrated Zero-IF Mobile TV Tuner RFIC for S-band CMMB Application, Yin Shi, Fa Foster Dai*, Jun Yan, Hua Xu, Xuelian Zhang, Heping Ma, Fang Yuan, Xin Guan and Richard Jaeger*, CAS Semiconductor Integration Technology Research Center, Suzhou, China, *Auburn University, Auburn, AL

We present a single-chip tuner RFIC for the newly established Chinese Mobile Multimedia Broadcasting (CMMB) standard. This mobile digital TV tuner covers the CMMB frequencies from 2.635GHz to 2.660GHz. Implemented in a 0.35um SiGe technology with 4mm2 die size, this tuner IC achieves noise figure of 2dB, input sensitivity of -100dBm, IIP3 of 17dBm, and total power of 162mW under a 2.8V supply.

8:30

11-1

Compact Modeling of Multiple-Gate MOSFETs (INVITED), Yuan Taur, Jooyoung Song and Bo Yu, University of California, San Diego, CA

This paper reviews recent development on compact modeling of multiple-gate MOSFETs. Starting with a core model based on the analytic potential solutions for the highly symmetric double-gate and surrounding-gate MOSFETs, an explicit solution to the implicit algebraic equations with high accuracy has been developed. With the addition of quantum, short-channel effects, and capacitance formulations, the core model for DG MOSFETs has been expanded into a full-blown compact model which has subsequently been calibrated and validated by FinFET hardware. In view of the various types of experimental multiple-gate MOSFETs developed, the DG and SG MOSFET models have been generalized to other less symmetric structures, including quadruple-gate, triple-gate, Ωgate, and II-gate devices.

9:20

11-2

Compact Modeling and Simulation of PD-SOI MOSFETs: Current Status and Challenges (INVITED), Jung-Suk Goo, Richard Williams*, Glenn Workman**, Qiang Chen, Sungjae Lee* and Edward Nowak*, Advanced Micro Devices, Sunnyvale, CA, *IBM Corporation, Essex Junction, VT, **Freescale Semiconductor Inc., Austin, TX

This paper reviews the status and challenges of the modeling Partially-Depleted Silicon-On-Insulator transistors.  Many challenges stem from the floating-body potential, which offers advantages in terms of performance and leakage, but presents complex electrical behavior. Circuit simulator considerations and the importance of model standardization are also highlighted.

10:25

11-3

Modeling Ionizing Radiation Effects in Solid State Materials and CMOS Devices (INVITED), Hugh Barnaby, Michael Mclain, Ivan Esqueda and X. J. Chen, Arizona State University, Tempe, AZ

A model is presented which enables the effects of ionizing radiation on CMOS devices to be simulated with closed form functions. The model adapts general equations for defect formation in SiO₂ films to facilitate calculations of damage in radiation sensitive shallow trench isolation oxides and “edge” leakage currents in MOSFETs.

11:15

11-4

Characterization, Simulation, and Modeling of FET Source/Drain Diffusion Resistance, Ning Lu and Bill Dewey*, IBM Semiconductor Research and Development Center, Essex Junction, VT, *IBM Electronic Design Automation, Fishkill, NY

We present a set of new SPICE models for the parasitic resistance in FET source and drain regions and a set of micro testing structures to measure and characterize diffusion resistance. Our FET source/drain diffusion resistance model has been verified with field solver simulation results, and is found to be very accurate over a wide range of parameter values. The testing structure approach has been validated using hardware data from a 65 nm SOI technology.

11:40

11-5

Analysis of the Impact of Interfacial Oxide Thickness Variation on Metal-Gate High-K Circuits, Minki Cho, Kingsuk Maitra* and Saibal Mukhopadhyay, Georgia Institute of Technology, Atlanta, GA, *Advanced Micro Devices, Albany, NY

A simulation methodology is developed to analyze the metal-gate high-K circuit variability due to variation in interfacial oxide layer thickness considering its impact on device electrostatics and transport. It is shown that, controlling interfacial oxide variation is very important to fully exploit the advantages of high-K metal gate technologies.

8:30

12-1

Time-Interleaved Analog-to-Digital Converters (INVITED), David Nairn, University of Waterloo, Ontario, Canada

This paper provides a tutorial review of time-interleaved analog-to-digital converters. After explaining the impact of mismatches on converter performance, current solutions to the mismatch problems are presented. The paper concludes with a summary of the current-state-of-the art for time-interleaved analog-to-digital converters.

9:20

12-2

A 12b 50MSPS 34mW Pipelined ADC, Hao Yu, Sing Chin and Bill Wong, National Semiconductor, Santa Clara, CA

A 12bit 50MSPS pipelined ADC is fabricated in 1.8V 0.18um CMOS process. Reference buffers without off-chip capacitors are implemented for 2Vpp input swing. Opamp-sharing and removal of S/H stage are utilized for low power dissipation. Occupying 1.81x0.76 mm^2, ADC achieves FOM of 0.27pJ/Step, SFDR of 86dBFS and ENOB of 11.3b.

9:45

12-3

Background ADC Calibration in Digital Domain, Cheongyuen Tsang, Yun Chiu*, Johan Vanderhaegen**, Sebastian Hoyos***, Charles Chen, Robert Brodersen and Borivoje Nikolic, University of California, Berkeley, CA, *University of Illinois, Urbana, IL, **Bosch Research and Technology Center, Palo Alton, CA, ***Texas A&M University, College Station, TX

A 100MS/s pipelined ADC is digitally calibrated by a slow sigma-delta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411kHz sinusoidal input, the peak SNDR improves from 28dB to 59dB and the SFDR improves from 29dB to 68dB. The complete 0.13um ADC SoC occupies a die size of 3.7mmx4.7mm, and consumes a total power of 448mW.

10:25

12-4

A 1.2v 11b 100Msps 15mW ADC Realized using 2.5b Pipelined Stage Followed by Time Interleaved SAR in 65nm Digital CMOS Process, Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath and Rakesh Malik, STMicroelectronics India

This paper describes an 11b ADC realized using a 2.5b pipelined stage followed by 9b time interleaved SAR. Presented ADC designed in 65nm CMOS process occupies 0.3mm2 area, achieves 59.1dB SINAD at 100Ms/s sampling frequency while dissipating 15mW power from 1.2V supply and resulting FOM is 0.20 pJ/step.

10:50

12-5

A 52mW 10b 210MS/s Two-Step ADC for Digital-IF Receivers in 0.13µm CMOS, Zhiheng Cao and Shouli Yan*, Qualcomm, San Diego, CA, *University of Texas, Austin, TX

A 10b 210MS/s two-step ADC has been implemented in 0.13µm digital CMOS with an active area of 0.38mm2. Using a proposed capacitor network implemented with small value interconnect capacitors which replaces the resistor ladder/multiplexer in conventional sub-ranging ADCs, and proposed offset canceling comparators, it achieves 74dB SFDR/55dB SNDR for 10MHz and 71dB SFDR/52dB SNDR for 100MHz inputs at 210MS/s while consuming 52mW from a 1.2V supply.

11:15

12-6

A 24GS/s 5-b ADC with Closed-Loop THA in 0.18um SiGe BiCMOS, Jaesik Lee, Joseph Weiner, Pascal Roux, Andreas Leven and Young-Kai Chen, Alcatel-Lucent, Murray Hill, NJ

A 5-b flash ADC with a closed-loop THA is implemented in 0.18-um SiGe BiCMOS. A global shunt feedback THA and a current-weighted comparator allow the ADC to achieve wide resolution bandwidth of 6.5GHz and high sampling rate up to 24GS/s. The ADC shows an SNDR of 28dB and an SFDR of 36dB with a 1GHz input sampled at 16GS/s. It consumes 3.3W from 3.6/3-V supplies and occupies 8.68mm2 silicon area.

8:30

13-1

A Biomedical Implantable FES Battery-Powered Micro-Stimulator (INVITED), Eusebiu Matei, Edward Lee, John Gord, Patrick Nercessian, Phil Hess, Howard Stover, Taihu Li and James Wolfe, Alfred Mann Foundation, Santa Clara, CA

The IC designs of an implantable battery-powered micro-stimulator for functional electrical stimulation applications are described. The ICs implement battery charging via external magnetic field through an on-chip rectifier with large field protection, a programmable stimulation control, a bio-potential signal sensor, a goniometry sensor, and a 400MHz transceiver for wireless communication.

9:20

13-2

CMOS LSI-based Multi-chip Flexible Retinal Prosthesis Device for Subretinal Implantation, Takashi Tokuda, Shigeki Sawamura, Yasuo Terasawa*, Yasuo Tano** and Jun Ohta, Nara Institute of Science and Technology, Nara, Japan, *NIDEK Co., Aich, Japan, **Osaka University, Osaka, Japan

A CMOS-based multi-chip flexible retinal stimulator was designed and demonstrated in animal experiments. The functionality and feasibility of the fabricated stimulator was confirmed. To apply the fabricated retinal stimulator for subretinal retinal stimulation, we have implemented a photosensing function on the stimulator, and demonstrated the basic functionality.

9:45

13-3

A CMOS TDC-Based Digital Magnetic Hall Sensor Using the Self Temperature Compensation, Young-Jae Min and Soo-Won Kim, Korea University, Seoul, Korea

A highly sensitive and temperature independent digital magnetic Hall sensor is presented. The MAGFET as the sensor device and bias, MPG and TDC circuits with the self temperature compensation and differential architecture are proposed. Because of the realization with digital circuits, this sensor can provide the simple and easy-design solution.

10:25

13-4

A Micro-Power Neural Spike Detector and Feature Extractor in .13um CMOS, Jeremy Holleman, Apurva Mishra, Chris Diorio and Brian Otis, University of Washington, Seattle, WA

We present a fully-integrated system for the detection and characterization of action potentials observed in extracellular neural recordings.  The circuit includes a spike detector, peak detectors to characterize the spikes, and an ADC.  It occupies .17mm2 in a .13um CMOS process and consumes 1uW from a 1V supply.

10:50

13-5

A Compact and Programmable High-Frequency Oscillator Based on a MEMS Resonator, Frederic Nabki, Faisal Ahmad, Karim Allidina and Mourad N. El-Gamal, McGill University, Montreal, Canada

This paper presents a compact programmable high-frequency oscillator based on a MEMS resonator and a high-resolution PLL. The resonator’s small size makes single package integration feasible. The oscillator tuning range is from 1.65GHz to 2GHz, and the high-resolution makes it possible to obtain a frequency stability of less than 0.125ppm.

8:30

14-1

Characterization and Design for Variability and Reliability (INVITED), Kevin Nowka, Sani Nassif and Kanak Agarwal, IBM Austin Research Laboratory, Austin, TX

Device variability due to sub-wavelength lithography, layout complexity, and random effects is impacting manufacturable design. Defects, aging, and noise must also be accounted for in design and manufacturing. Characterization structures to quantify these effects, measured behaviors, the resulting models, and design and tools mitigation actions are presented in this paper.

9:20

14-2

A 9Gbit/s Serial Transceiver for On-chip Global Signaling over Lossy Transmission Lines, JunYoung Park, Joshua Kang, Sunghyun Park and Michael Flynn, University of Michigan, Ann Arbor, MI, Qualcomm, San Diego, CA, and Campbell, CA

A 9Gbit/s serial link transceiver for on-chip global signaling is presented. A transmitter serializes the parallel 8b 1.125Gbyte/s data over a 5.8mm lossy on-chip transmission line; the receiver de-serializes the data with a digitally tuning interpolator. The prototype transceiver, implemented in 0.13um 8M CMOS, achieves 9Gbit/s with four pre-defined data patterns and a measured BER is less than 10-10.

9:45

14-3

A 28mW OFDM Baseband Receiver Chip for DVB-T/H with All Digital Synchronization, Ting-Chen Wei, Wei-Chang Liu, Chi-Yao Tseng*, Syu-Siang Long*, Shyh-Jye Jou and Muh-Tian Shiue, National Chiao Tung University, Taiwan, ROC, National Central University, Taiwan, ROC

An OFDM baseband receiver chip for DVB-T/H application is proposed in this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset and ± 50 subcarrier spacing carrier frequency offset in multipath environment. By using 0.18µm CMOS process, the power consumption is 28mW at 1.45 V, 40MHz.

10:25

14-4

Nonvolatile Magnetic Flip-Flop for Stanby-power-free SoCs, Noboru Sakimura, Tadahiko sugibayashi, Ryusuke Nebshi, and Naoki Kasai, NEC Corporation, Kanagawa, Japan]

A nonvolatile Magnetic Flip-Flop (MFF) for SoC design libraries has been developed using a unique MRAM process. The MFF maximum frequency was estimated to be 3.5 GHz, which is comparable to that of a CMOS DFF. The measured performance of MFF was sufficiently high to demonstrate the potential of MFFs.

10:50

14-5

A Fully Integrated Pulsed-LASER Time-of-Flight Measurement System with 12ps Single-Shot Precision, Tino Copani, Bert Vermeire, Anuj Jain, Habib Karaki, Kailash Chandrashekar, Sushmit Goswami, Jennifer Kitchen, Hoon Hee Chung, Ilker Deligoz, Bertan Bakkaloglu, Hugh Barnaby and Sayfe Kiaei, Arizona State University,

A monolithic time-of-flight measurement system is presented in this paper. The circuit comprises an optical receiver front-end, pulse amplitude detectors and time-to-digital converter. The IC is fabricated in a 0.18um BiCMOS process. The system achieves a 12ps accuracy and a measurement range of 188us.

11:15

14-6

A Low-Power IC Design for the Wireless Monitoring System of the Orthopedic Implants, Hong Chen, Jia Chen, Yi Chen, Ming Liu, Chun Zhang and Zihua Wang, Tsinghua University

This paper proposes an architecture of the wireless monitoring system for the monitoring of the orthopedic implants. The Radio Frequency circuits and the power circuit have been taped out and tested. The circuits including RF circuits, Analog Digital Converter, and Micro control Unit have been implemented in 0.18u;m CMOS process.

11:40

14-7

Tessellation-Enabled Shader for a Bandwidth-Limited 3D Graphics Engine, Kyusik Chung, Chang-Hyo Yu, Donghyun Kim and Lee-Sup Kim, KAIST, Daejeon, Rep. of Korea

A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is implemented with 6.2% additional logic to a conventional vertex shader for a mobile 3D graphics engine. A symmetric dual-core TES is fabricated using 0.18um CMOS technology and processes 120Mvertices/s at 100MHz while consuming 272mW of power.

2:05

15-1

Lithography Options for the 32nm Half Pitch Node and Beyond (INVITED), Kurt Ronse, Philippe Jansen, Roel Gronheid, Eric Hendrickx, Mireille Maenhoudt, Mieke Goethals and Geert Vandenberghe, IMEC, Leuven, Belgium

There are three major lithography options for high volume manufacturing at the 32nm half pitch node: 193nm immersion lithography with high index materials, 193nm double patterning and EUV lithography. The pros and cons of these options are discussed. The extendibility of these options is important for the final choice.

2:55

15-2

45nm High-k + Metal Gate Strain-Enhanced CMOS Transistors (INVITED), Chris Auth, Intel Corporation, Hillsboro, OR

At the 45nm technology node, high-k + metal gate transistors have been introduced into high volume manufacturing. The introduction of a high-k gate dielectric enabled a reduction in Tox while reducing gate leakage. Dual-band edge workfunction metal gates eliminated polysilicon gate depletion and provided compatibility with the high-k gate dielectric.

4:00

15-3

Will BiCMOS  Stay Competitive for mmW Applications (INVITED), Patrice Garcia, Alain Chantre, Sebastien Pruvost, Pascal Chevalier, Sean Nicolson*, David Roy, Sorin Voinigescu*, Christophe Garnier, STMicroelectronics, Crolles, France, *University of Toronto, Toronto, Canada

4:50

15-4

Microelectronics for the Real World: "Moore" versus "More than Moore" (INVITED), John Kent and Jagdish Prasad, ON Semiconductor, Pocatello, ID

Memories and microprocessors require silicon based CMOS technologies that follow “Moore’s” law. However, a new trend of functional diversification is emerging that does not necessarily scale but provides additional value to the end customer. This functional diversification is being called “More-than-Moore”. This approach allows for non-digital functionalities such as RF, power control, passive components, sensors and actuators to migrate from the system board level into a package level (SiP) or chip level (SoC) implementation. The objective of “More-than-Moore” is to incorporate digital and non-digital functionality into compact systems. “More-than-Moore” technologies are application specific and focus on the interface between the “Analog” and the digital world. In this paper we will discuss the applications of “More-than-Moore” concept and its utility in real life.

2:05

16-1

A 512-KB Level-2 Cache Design in 45 nm for sub-2W Low Power IA Processor Silverthorne, Mohammed Taufique, Alex Okpisz, Haseeb Ahmed, John Riley, Mohammad Hasan, Gian Gerosa, Intel Corporation, Austin, TX

A self-timed, single cycle throughput, phase based 512KB L2 cache design in 45nm CMOS process for a low power IA core is presented. Dynamic latch is incorporated to narrower pulse for the sense amplifier. Power gated WL driver, SRAM sleep, floating the bit lines and tri-state write driver are implemented to reduce power. The design operates up to 2.5GHz and 1.2GHz at 1.0V and 0.75V in Silicon respectively.

2:30

16-2

A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode, Tae-Hyoung Kim, Jason Liu and Chris H. Kim, University of Minnesota, Minneapolis, MN

A voltage scalable 0.26V, 64kb 8T SRAM with 512 cells per bitline is implemented in a 130nm CMOS process. A marginal bitline leakage compensation scheme, floating write bitline and read bitline, auto wordline pulse width control, and a deep sleep mode were proposed for Vmin lowering and power reduction.

2:55

16-3

Compensation of Systematic Variations Through Optimal Biasing of SRAM Wordlines, Andrew Carlson, Zheng Guo, Liang-Teck Pang, Tsu-Jae King Liu and Borivoje Nikolic, University of California, Berkeley, CA

Increasing process variability is slowing SRAM scaling by reducing both read and write margins. A sensor circuit is presented that optimizes the read / write tradeoff in the presence of process, voltage, and temperature variations in a low-power 45nm test chip to track the optimal wordline bias within 30mV.

3:20

16-4

Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines, Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai and Lawrence T. Pileggi, Carnegie Mellon University, Pittsburgh, PA

A configurable replica bitline for controlling sense-amplifier enable (SAE) timing for small-swing bitline SRAMs is described. An exponential reduction in SAE timing variation is enabled by statistical selection of driver cells, which can provide 14x reduction in timing uncertainty. We present measured results from a 90nm CMOS 64kb SRAM testchip.

4:00

16-5

A 135mV 0.13uW Process Tolerant 6T Subthreshold DTMOS SRAM in 90nm Technology, Myeong-Eun Hwang and Kaushik Roy, Purdue University, West Lafayette, IN

We propose a DTMOS based 6T SRAM suitable for variation-tolerant subthreshold operation. For robust memory peripherals, we apply P/N-ratio modulation technique. DTMOS SRAM fabricated in 90nm technology operates down to 135mV consuming 0.13uW and achieves 200% improvement in read SNM at iso-area compared to the conventional SRAM at 200mV.

4:25

16-6

Robust Ultra-Low Voltage ROM Design, Mingoo Seok, Scott Hanson, Jae-Sun Seo, Dennis Sylvester and David Blaauw, University of Michigan, Ann Arbor, MI

SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging as the supply voltage is reduced aggressively. In this paper, three different ROM topologies are investigated and compared for ultra-low voltage operation. A simple method to estimate the theoretical robustness at low voltage is proposed and applied to the ROM topologies. A test circuit fabricated in a carefully-selected 0.18um CMOS technology reveals that our proposed static NAND ROM structure improves performance by 26X, energy by 3.8X and lowest functional supply voltage by 100mV over a conventional dynamic NAND ROM.

4:50

16-7

A Million Cycle 0.13um 1Mb Embedded SONOS Flash Memory Using Successive Approximated Read Calibration, Nan Wang, Xiang Yao, Yu Lei, Guoyou Feng, Qiaohua Dong, Liang Xu, Lu Guo and Zi Wang, NEC Electronics Company, Ltd.

A 1Mb embedded SONOS Flash macro, implemented in 0.13um logic compatible process, has improved reliability with power-on Successive Approximated Read Calibration (SARC).  Voltage Divided High Voltage Tolerance (VDHVT) method is designed to reduces word-line decoder area using 1.8V transistors. The Flash macro achieves 20 years’ retention and one million cycling.

2:05

17-1

A Wide Tuning Range (1 GHz-to-15 GHz) Fractional-N All-Digital PLL in 45nm SOI, Alexander Rylyakov, Jose Tierno, George English*, Michael Sperling* and Daniel Friedman, IBM T.J. Watson Research Center, Yorktown Heights, NY, *IBM, Poughkeepsie, NY

An all static CMOS all-digital fractional-N PLL has a wide tuning range and supports multiplication factors of up to 1,000x. At 0.7V (9.7mW), 125C the period jitter of the 4.12GHz clock (206MHz reference) is 2.2ps rms, 22.7ps pp. The area of the PLL is 175um x 160um.

2:30

17-2

Clocking Circuits for a 16Gb/s Memory Interface, Ting Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun, TJ Chin, Jie Shen, Rich Perego and Ken Chang, Rambus Inc., Los Altos, CA

8GHz clocking circuits for a 16Gb/s/pin asymmetric memory interface [1] are described. A combination of an LC-PLL and a ring-PLL achieves improved jitter performance for multiple phase outputs with a wide frequency range. A direct phase mixer and a digitally controlled duty-cycle corrector (DCC) are time-multiplexed between transmitter (TX) and receiver (RX), thereby reducing area and power. The prototype chip implemented in a 65nm CMOS technology has measured 734fs RJ (rms) at the TX output when operating at 16Gb/s.

2:55

17-3

A 1V 15.6mW 1-2GHz -119dBc/Hz @ 200kHz clock multiplying DLL, Sander Gierkink, Conexant Systems, Red Bank, NJ

A 0.11mm2 90nm 15.6mW 1V 1-2GHz clock multiplier has a lock-detect that switches it from PLL to DLL and reconfigures the loop filter. The number of delay stages is programmable to 8-10-12-14-16. Multiplication range is 2-64. With 80MHz reference, L(200kHz) is -125dBc/Hz & -119dBc/Hz at 0.92 & 1.92GHz output respectively.

3:20

17-4

A 0.5-to-2.5GHz Supply-Regulated PLL with Noise Sensitivity of -28dB, Abhijith Arakali, Srikanth Gondi*, and Pavan Kumar Hanumolu, Oregon Stte University, Corvallis, OR, *Kawasaki Microelectronics America, Inc., San Jose, CA

A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. The prototype PLL, incorporating a novel regulator, is fabricated in a  0.18um digital CMOS process and operates from 0.5 to 2.5GHz. At 1.5GHz, the proposed PLL achieves a worst-case noise sensitivity of -28dB (0.5rad/V), an improvement of 20dB over conventional solutions, while consuming 2.2mA from a 1.8V supply.

4:00

17-5

20 GHz Low Power QVCO and De-skew Techniques in 0.13um Digital CMOS, Masum Hossain and Anthony Chan Carusone, University of Toronto, Toronto, Canada

A novel VCO topology is proposed that combines the low power of –gm oscillators with the inherent buffering of Colpitts oscillators. Using this topology, a quadrature VCO (QVCO) was implemented in 0.13 um digital CMOS consuming 32 mW at 20 GHz with just over 10% tuning range. The measured phase noise of the QVCO at 20.17 GHz is -102.41 dBc/Hz at 1 MHz offset. Because the load is isolated from the tank, the QVCO can directly drive 50-Ohm impedances or large capacitive loads with no additional buffering. A technique to use the QVCO to deskew clocks is also presented whereby the QVCO accepts a small forwarded clock amplitude of 20 mV, and provides a 200 mV peak-to-peak differential clock output with linear control of the phase over the complete range, 0-360.

4:25

17-6

A 3 GHz Spread Spectrum Clock Generator for SATA Applications Using Chaotic PAM Modulation, Fabio Pareschi, Gianluca Setti and Riccardo Rovatti*, University of Ferrara, Ferrara, Italy, *University of Bologna, Bologna, Italy

This paper proposes a prototype of a Spread Spectrum Clock Generator which is the first known specifically meant for 3 GHz SATA-II applications. The modulation is obtained from a fractional PLL which employs a Delta-Sigma modulator. A further innovative aspect of our work is that our prototype takes advantage of a chaotic PAM as driving signal, instead a triangular signal as in all spread spectrum generators proposed in Literature for SATA-II. The circuit prototype has been designed in 0.13 um CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW=100 kHz.

4:50

17-7

A 1.5 GHz Spread Spectrum Clock Generator with 5000ppm Piecewise Linear Modulation, Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yontae Kim and Chulwoo Kim, Korea University

A spread spectrum clock generator is implemented in a 0.18um CMOS process employing the proposed modulation profile to reduce EMI significantly with simple implementation. A high resolution fractional divider is proposed as well. A peak power reduction level of 14.2dB with 5000ppm down spreading and 27.88pspp of jitter are measured.

5:15

17-8

A 8x5 Gb/s Source-Synchronous Receiver with Clock Generator Phase Error Correction, Ankur Agrawal, Pavan Kumar Hanumolu* and Gu-Yeon Wei, Harvard University, Cambridge, MA, *Oregon State University, Corvallis, OR

This paper describes the design and implementation of a 8x5Gb/s source-synchronous receiver in a 0.13 micron CMOS technology. The receiver employs a cascaded-DLL architecture that preserves the jitter on the received clock to enhance jitter tolerance bandwidth. Techniques are proposed to correct phase spacing mimatch in DLLs that reduces the error by > 40%.

2:05

18-1

Millimeter-wave CMOS Integrated Circuits for Gigabit WPAN Applications (INVITED), Tian-Wei Huang and Huei Wang, National Taiwan University, Taiwan, ROC

60-GHz gigabit wireless personal area network (WPAN) is an attractive application for next-generation dual-mode broadband wireless network.  The CMOS technologies enable the low-cost manufacturability and system-on-chip (SoC) integration for 60-GHz low-power mobile devices.  This paper compares the RF performance of the reported 60-GHz CMOS transceivers, and also discusses the architecture design trade-offs between performances and dc power consumption.

2:55

18-2

A Zero-IF 60GHz Transceiver in 65nm CMOS with > 3.5Gb/s Links, Alexander Tomkins, Ricardo A. Aroca, Takuji Yamamoto*, Sean T. Nicolson, Yoshiyasu Doi* and Sorin P. Voinigescu, University of Toronto, Toronto, Canada, *Fujitsu Laboratories, Kawasaki, Japan

A transceiver employing direct BPSK modulation, 60GHz LO tree, static divider, and Gilbert-cell mixer occupies 1.28x0.81mm2.  With 5.6dB noise figure, 14.7dB conversion-gain and +2.7dBm Pout, the transceiver was characterized over 5-85C, 1-1.2V power-supply and process splits.  A TXRX link over 2m at 3.5Gb/s data-rates was demonstrated without ADCs and IQ-mixer.

3:20

18-3

Low-Cost Fully Integrated BiCMOS Transceiver for Pulsed 24-GHz Automotive Radar Sensors, Laurence Moquillon, Patrice Garcia, Sebastien Pruvost, Stephane Le Tual, Maxime Marchetti, Laurent Chabert, Nicole Bertholet, Angelo Scuderi*, Salvatore Scaccianoce*, Alberto Serratore*, Nicolo Ivan Piazzese*, Cedric Dehos** and Domique Morche**, STMicroelectronics, Crolles, France, *Catania, Italy, **CEA-LETI,Grenoble, France

This work presents the performance of a 24-GHz transceiver for automotive short-range radar.  Complying with the pulsed radar sensor requirements, this single-chip is the first silicon realization with this high-level of integration. The single-chip results were obtained at 24 GHz using a standard 0.13um BiCMOS SiGe 170GHz fT featuring 1.7V BVceo. This allows a receive path of 47 dB gain with 3 dBDSB noise figure providing a dynamic range of 31 dB. In the transmission section, 1-ns pulses modulated at 24 GHz are also obtained using an RF switch, which is able to deliver a continuous wave output power of 0dBm.

4:00

18-4

A 0.13um CMOS Fully Differential Receiver with On-Chip Baluns for 60GHz Broadband Wireless Communications, Chao-Shiun Wang, Juin-Wei Huang, Kun-Da Chu and Chorng-Kuang Wang, National Taiwan University, Taiwan, ROC

This paper presents a fully differential receiver with on-chip baluns for 60GHz broadband wireless applications. This design consists of on-chip baluns, gm-boosted current-reuse low-noise amplifier (LNA), sub-harmonic dual-gate down conversion mixer, second IF mixer and baseband gain stage. Fully differential circuit technique is adopted to obtain good common mode performance. The gm-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration issues associated with previous solutions. The sub-harmonic dual-gate down conversion mixer will prevents the issue of the third harmonic of the LO as well. The measured conversion gain and input P1dB of the proposed receiver are 30 dB and -27 dBm, respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The proposed 60GHz receiver dissipates 44 mW with a 1.2 V supply voltage. The fully differential receiver with the on-chip baluns is imple¬mented in a standard 0.13um 1P8M+ RF CMOS technology.

4:25

18-5

A Low power 20 GHz 1.5 Gb/s CMOS Injection-Pulling FSK Modulator and Frequency Discriminator for 60GHz Links, Shon-Hang Wen, Chao-Shiun Wang and Chorng-Kuang Wang, National Taiwan University, Taiwan, ROC

This paper presents a low power frequency shift keying (FSK) modulator and demodulator (MODEM) that can support over than 1 Gb/s data rate for high-speed multimedia data communications. Compared with open-loop direct modulation of a voltage-controlled oscillator (VCO), the direct injection-pulling of a VCO enables the high speed FSK modulation without suffering frequency drift problem. The FSK discriminator uses injection-locked technique to perform frequency to phase transformation with low power consumption. Due to the lack of delay-dependent term in this new transformation, the accurate delay control circuits can be removed. Realized in the 0.13-um CMOS technology, the FSK MODEM can achieve maximum data rate of 1.5 Gb/s. The power consumption of core modulator and demodulator is 14.4 mW.

4:50

18-6

A 24/77GHz Dual-Band BiCMOS Frequency Synthesizer, Vipul Jain, Babak Javid and Payam Heydari, University of California, Irvine, CA

The design of the first  millimeter-wave dual-band frequency synthesizer in a 0.18µm SiGe BiCMOS technology  is presented. All circuits except the voltage controlled oscillators (VCOs) are shared between the two bands. A W-band divide by 3 frequency divider is used to simplify division-ratio reconfiguration. The 0.9mm2 synthesizer chip exhibits a locking range of 23.7-26.9GHz/75.65-78.6GHz with a power consumption of 95mW from 2.5/1.8V supplies. The phase noise at 1MHz offset from the carrier is less than -100dBc/Hz in both bands. The proposed frequency synthesizer is suitable for integration in transceivers for K/W band automotive radars and 94GHz imaging.

5:15

18-7

An X/Ku-Band Frequency Synthesizer Using A 9-Bit Quadrature DDS, Xuefeng Yu, Fa Foster Dai, Dayu Yang, J. David Irwin, Richard C. Jaeger, Auburn University, Auburn, AL

This paper presents an X/Ku-band fine-tuning frequency synthesizer using a quadrature DDS implemented in a 0.18um SiGe BiCMOS technology. The frequency synthesizer comprises a 9-bit quadrature DDS, an 11.7GHz quadrature VCO and image rejection mixers. The outputs of the quadrature DDS are down-converted to 9.4~11.7GHz and up-converted to 11.7~14.0GHz, respectively. The die area of the synthesizer is 3.0x3.0mm2 and the power consumption is 2.6W under a 3.3V supply. The chip is measured with a 48-pin leadless free ceramic package and external cooling.

T-01

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology, Xiaolei Zhu, Yanfei Chen, Masaya Kibune*, Yasumoto Tomita*, Takayuki Hamada*, Hirotaka Tamura*, Sanroku Tsukamoto* and Tadahiro Kuroda, Keio University, Yokohama, Japan, *Fujitsu Laboratories Ltd., Kawasaki, Japan

A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 x 65 um2 and consumes 380 uW.

T-02

A Low-Voltage OP Amp with Digitally Controlled Algorithmic Approximation, Dong-Woo Jee, Seung-Jin Park, Hong-June Park and Jae-Yoon Sim, Pohang University of Science and Technology, Kyungbuk, Korea

This paper presents a new architecture of digitally controlled algorithmic OP amp suitable for scaled CMOS technologies. With inverter-based gain stages and digitally-assisted damping control, the amplifier achieves high-gain and wide input/output ranges even at the minimally allowable supply voltage by digital circuits. The amplifier, implemented in a standard 0.18 um CMOS, shows a DC gain of 73 dB and 95 % settling time of 41 ns at 0.5 V step input.

T-03

A 105.5 dB, 0.49 mm2 Audio Sigma Delta Modulator using Chopper Stabilization and Fully Randomized DWA, Yi-Gyeong Kim, Min-Hyung Cho, Kwi-Dong Kim, Jong-Kee Kwon and Jongdae Kim, ETRI, Daejeon, Korea

An audio sigma-delta modulator achieves 105.5dB dynamic range. In order to minimize the contribution of the flicker noise, chopper stabilization techniques are used in the first integrator and in the reference buffer. The fully randomized DWA is used as a DEM. The chip was fabricated in 0.13 um CMOS technology (I/O devices) and occupies a small chip area of 0.49mm2.

T-04

An Ultra Low Power 1V, 220nW Temperature Sensor for Passive Wireless Applications, Yu-Shiang Lin, Dennis Sylvester and David Blaauw, University of Michigan, Ann Arbor, MI

This work presents a low power temperature sensor that is suitable for passive wireless systems. The test chip is fabricated with a 0.18um CMOS technology and the total area is 0.05mm2. With temperature inaccuracy of -1.6°C/+3°C from 0°C to 100°C , the temperature sensor consumes only 220nW under room temperature.

T-05

A 9-Bit Configurable Current Source with Enhanced Output Resistance for Cochlear Stimulators, Song Guo, Hoi Lee and Philipos Loizou, University of Texas at Dallas, Richardson, TX

This paper presents a configurable current source for cochlear stimulators.  A switchable multi-bias active-cascode architecture is developed to provide a 9-bit output current in a small implementation area.  A stacking MOS structure enables the current source to achieve high output resistance and large voltage compliance.  Implemented in a standard 0.35um CMOS process, the current source can source a maximum 1mA current, provide >4.77V voltage compliance under a 5V supply and achieve >50MΩ output resistance in 0.26mm².

T-06

Super-Resolution: Imaging beyond the Pixel Size Limit, Tamer Elkhatib and Khaled Salama, Rensselaer Polytechnic Institute, Troy NY

We present a high resolution imaging technique independent of an image sensor's pixel size. This super-resolution is achieved by integrating a nano-aperture patterned in the first metal layer within the pixel using a standard CMOS process, then scanning the detection focal plane with a sub-micron. To experimentally verify the operation of our technique, we fabricated a standard 3-Transistors (3T) active pixel sensor with integrated nano-apertures in a 0.13um CMOS technology.

T-07

Polysilicon Vertical Actuator Powered with Waste Heat, Jorge Varona, Margarita Tecpoyotl-Torres and Anas Hamoui*, Universidad Autonoma del Estado de Morelos, Mexico, *McGill University, Montreal, Canada

Traditional thermal actuators require an electric current to generate heat by Joule effect and obtain motion via thermal expansion. This work offers a simplified polysilicon actuator designed to operate with an external heat source and scavenge heat from the surrounding medium. Analytical and experimental results are provided to illustrate performance.

T-08

Low Noise uWatt Interface Circuits for Wireless Implantable Real-Time Digital Blood Pressure Monitoring, Peng Cong, Wen Ko and Darrin Young, Case Western Reserve University, Cleveland, OH

A miniature pressure sensing microsystem, including an MEMS capacitive pressure sensor and low-noise µWatt capacitance-to-voltage converter followed by an 11-bit cyclic ADC, achieves a sensing resolution of 0.1 mmHg over a 1 kHz bandwidth with a dynamic range of 59 dB. The sensing electronics consume 18 µA from a 2V supply.

T-09

A Flexible Decoder IC for WiMAX QC-LDPC Codes, Tzu-Chieh Kuo and Alan Willson, University of California, Los Angeles, CA

A 0.18-um QC-LDPC decoder IC is presented. It occupies a 2.22 mm x 1.52 mm core area and dissipates estimated 165 mW. It is 53% smaller in size, 86% lower in complexity, and has better energy efficiency than other published WiMAX LDPC decoder ASICs, to the best of our knowledge.

T-10

Minimizing the Supply Sensitivity of CMOS Ring Oscillator by Jointly Biasing the Supply and Control Voltage, Ping-Hsuan Hsieh, Jay Maxey* and Chih-Kong Ken Yang, University of California, Los Angeles, CA, *Texas Instruments, Dallas, TX

A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage.  The technique can supplement a number of common supply rejection techniques.  The proposed CMOS ring oscillator is designed and implemented with a charge-pump based phase-locked loop in 65-nm technology to demonstrate the robustness against the supply fluctuation.  Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 4-GHz output clock is reduced from 10.66-ps to 5.04-ps while subject to switching noise with magnitude of 2.5% of the supply voltage at 150-MHz.  Furthermore, more than 4.5x of reduction in the power consumption is achieved.

T-11

The Superchip: Innovative Teaching of IC Design and Manufacture, Peter Wilson, Reuben Wilcock, Matthew Swabey, Iain McNally and Bashir Al-Hashimi, University of Southampton, Southampton, UK

In this paper we describe how through intelligent chip architecture, a large cohort (~100 students) of undergraduates can be given effective practical insight into IC design by designing and manufacturing their own individual ICs. To achieve this, the “Superchip” has been developed, which allows (without excessive cost in terms of time or resources) multiple student designs to be fabricated on a single IC, and encapsulated in a standard package. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. The paper provides details of the chip architecture, test regime, test vectors, and an example design.

T-12

A 3D Graphics Processor with Fast 4D Vector Inner Product Units and Power Aware Texture Cache, Jae-Sung Yoon, Donghyun Kim, Chang-Hyo Yu and Lee-Sup Kim, KAIST, Daejeon, Korea

A 3D graphics processor for mobile application is presented. A dual-core dual-issue system, a fast 4D vector inner product arithmetic unit, an internal bus system and a configurable texture cache technique are used to achieve 143Mvertices/s and 2.3 Gtexels/s consuming the power of 367mW.

T-13

Timing Yield Enhancement Through Soft Edge Flip-Flop Based Design, Young Min Park, Carlos Tokunaga, Michael Wieckowski, Dong Woon Kim, Zhiyoong Foo, Dennis Sylvester and David Blaauw, University of Michigan, Ann Arbor, MI

The first evaluation of a soft-edge flip-flop is presented as an alternative to useful-skew and latch-based designs for variation compensation in a 16-bit 8-tap FIR filter in 0.13um CMOS.  An 11.2% performance improvement was achieved over a standard hard edge data flip-flop (9.2% when post-silicon useful-skew is applied).

T-14

Power Minimization of Logic Circuits by Global Optimization of Fine Grain Body Bias, Yasumi Nakamura, David Levacq, Limin Xiao, Takuya Minakawa, Taro Niiyama, Makoto Takamiya and Takayasu Sakurai,  University of Tokyo, Tokyo, Japan

A fine grain body bias control to compensate both the process and design variations is proposed. The test chip was fabricated in 90nm CMOS process. The proposed global optimization scheme reduced power by 23% compared with “as fabricated” and by 11% compared with conventional local optimization. Also, the proposed global optimization scheme reduced power by 5~9% within 20 test iterations with simulated annealing algorithm. This is a promising approach for the power efficient processors at a reasonable testing cost.

T-15

A DC-DC Converter with a Dual VCDL-based ADC and a Self-Calibrated DLL-based Clock Generator for an Energy-Aware EISC Processor, Sunghwa Ok, Jungmoon Kim, Gilwon Yoon, Hyunho Chu, Jaegeun Oh, Seon Wook Kim and Chulwoo Kim, Korea University, Seoul, Korea

This paper describes a dynamic voltage and frequency scaling (DVFS) scheme for the dynamic power management (DPM) of the extendable instruction set computing processor. The DVFS circuit comprises a digitally-controlled DC-DC buck converter with a dual VCDL-based ADC and a low-power and low-jitter DLL-based clock generator with self-calibration.

T-16

Active Autonomous AC-DC Converter for Piezoelectric Energy Scavenging Systems, Enrico Dallago, Daniele Miatton, Giuseppe Venchi, Valeria Bottarel*, Giovanni Frattini*, Giulio Ricotti* and Monica Schipani*, University of Pavia, Pavia, Italy, *STMicroelectronics, Milan, Italy

A novel driving circuitry for an active AC DC converter used into Piezoelectric Energy Scavenging Systems is described. It is tolerant with respect to the process variations and uses a fraction of the harvested energy to supply itself. Experimental results of a chip, diffused in 5V CMOS STMicroelectronics technology, are presented.

T-17

A 10Gb/s Receiver with Linear Backplane Equalization and Mixer-Based Self-Aligned CDR, Simone Erba, Massimo Pozzoni, Matteo Pisati, Riccardo Brama*, Davide Sanzogni, Emanuele Depaoli, Paolo Viola and Francesco Svelto**, STMicroelectronics, Pavia, Italy, **Universita degli Studi di Pavia, Pavia, Italy, *Universita di Modena e Reggio Emilia, Reggio Emilia, Italy

A 65nm CMOS receiver including a tapered chain linear equalization and a mixer based clock recovery circuit capable of SSC tracking is presented. The proposed architecture works up to 10 Gb/s with transmission channels with more than 20dB loss at Nyquist, while consuming 110mA and occupying 0.25mm2.

T-18

A 12.5-Gbps, 7-bit Transmit DAC with 4-Tap LUT-based Equalization in 0.13µm CMOS, Hayun Chung, Andrew Liu and Gu-Yeon Wei, Harvard University, Cambridge, MA

A 12.5-Gbps transmitter with a LUT-based equalizer to compensate for within-die imperfections is proposed. Proposed equalization technique accommodates timing offsets in the multiphase clocks while LUT code remapping compensates for other mismatch effects. Experimental results show the equalizer can significantly improve the signal integrity of an otherwise closed eye.

T-19

Active Deskew in Injection-Locked Clocking, Lin Zhang, Berkehan Ciftcioglu and Hui Wu, University of Rochester, Rochester, NY

This paper presents an injection-locked clock (ILC) distribution system with a new active deskew mechanism based on the built-in phase tuning of injection-locked oscillators (ILO). The proposed technique removes the required deskew delay lines and associated power dissipation, clock latency and jitter accumulation in conventional active deskew schemes.

T-20

A 53 GHz DCO for mm-Wave WPAN, Raffaella Genesi, Francesco M. De Paola and Danilo Manstretta, Universita degli Studi di Pavia, Pavia, Italy

A digitally-controlled oscillator for mm-wave WPAN is demonstrated for the first time. Low phase noise is achieved adopting an efficient complementary topology and optimizing the capacitor array. Measured oscillation frequency ranges from 51.3 to 53.3 GHz with 1.8MHz resolution, phase noise is -116.5dBc/Hz at 10MHz and the figure-of-merit is -187.2dBc/Hz

T-21

Twisted Inductors for Low Coupling Mixed-Signal and RF Applications, Nathan Neihart, David Allstot, Matt Miller* and Pat Rakers*, University of Washington, Seattle, WA, *Freescale Semiconductor Inc., Lake Zurich, IL

Parasitic magnetic coupling is a major design challenge for integrated circuit designers. This paper introduces a twisted winding scheme for inductors that increases the localization of the magnetic field, reducing parasitic magnetic coupling by 3100X and the edge-to-edge spacing of inductors by 10X. These results are validated in 0.18um CMOS.

T-22

A Common-Base Linear RF Power Amplifier for 3G Cellular Applications, Flavio Avanzo, Francesco M. De Paola and Danilo Manstretta, Universita degli Studi di Pavia, Pavia, Italy

A common-base linear power amplifier is presented that can sustain output voltages in excess of BVCEO. The chip, implemented in a 0.25um SiGe:C technology, occupies 2.7mm2. The P-1dB is 27 dBm at 4.5 V supply with a power gain of 20 dB and a power-added efficiency of 33%.

T-23

Design of Low Power CMOS Ultra-Wideband 3.1-10.6 GHz Pulse-Based Transmitters, Kuan-Yu Lin and Mourad El-Gamal, McGill University, Montreal, Canada

The design of two low power CMOS ultra-wideband pulse-based transmitters is reported. The first transmitter utilizes a gated ring oscillator, an NMOS switch, and a filter to generate a full-band UWB signal. The second transmitter multiplies a carrier and a triangular signal to generate a low side-band UWB signal.

8:30

19-1

Energy-efficient Wireless Front-end Concepts for Ultra Low Power Radio (INVITED), John R. Long, Wanghua Wu, Yunzhi Dong, Yi Zhao, Mihai A.T. Sanduleanu*, John F.M. Gerrits** and Gerrit van Veenendaal***, Delft University of Technology, Delft, The Netherlands, *Philips Research, Eindhoven, The Netherlands, **CSEM, Neuchatel, Switzerland, ***NXP Semiconductors, Eindhoven, The Netherlands

Two ultra low power wireless concepts are described in this paper. A high data rate receiver demonstrator consisting of LNA, sub-harmonic I/Q mixer and transimpedance IF amplifiers realizes an energy consumption of 1.75 nJ/bit at 10Mbit/s in the 17GHz band. A high-band FM-UWB receiver demonstrator, which achieves a measured sensitivity of -84.3dBm at 100kbit/s while consuming just 6mW is also described.

9:30

19-2

A 0.4 nJ/b 900MHz CMOS BFSK Super-Regenerative Receiver, James Ayers, Kartikeya Mayaram and Terri Fiez, Oregon State University, Corvallis, OR

An ultra low-power BFSK super-regenerative receiver has been designed and fabricated in a 0.18 um CMOS process.  System level operation and low-power design techniques are presented.  At 1 Mb/s the receiver consumes 0.4 nJ/b making it the lowest energy integrated super-regenerative receiver to date.

9:45

19-3

A 900-MHz Low-Power Transmitter With Fast Frequency Calibration For Wireless Sensor Networks, Napong Panitantum, Kartikeya Mayaram and Terri Fiez, Oregon State University, Corvallis, OR

A low-power transmitter designed for wireless sensor networks operating in a 900-MHz ISM band has been fabricated in 0.18-/spl mu/m CMOS technology.  The transmitter has a power efficiency as high as 26% while radiating an output signal of -2.9 dBm.  It supports both OOK and BFSK modulation.  A fast frequency calibration is developed to reduce the RF tuning time down to 36 /spl mu/s and thus further minimize the overall energy consumption.

10:25

19-4

A 3.5-mW 15-Mbps O-QPSK Transmitter for Real-time Wireless Medical Imaging Applications, Yao-Hong Liu and Tsung-Hsien Lin, National Taiwan University, Taiwan, ROC

A 400-MHz phase-mux-based O-QPSK transmitter (TX) for medical imaging applications is presented in this paper. The modulation signal is generated by selecting one of the four quadrature phases to the TX output via a proposed Phase MUX. An inverter-type power amplifier is utilized for it is compatible with the quasi constant-envelop nature of the O-QPSK modulation. Fabricated in a 0.18-um CMOS process, the whole TX draws 2.9 mA from a 1.2-V supply. With a maximum 15-Mbps data rate, the TX achieves an energy efficiency of 0.23 nJ/bit and delivers an output power up to -7 dBm.

10:50

19-5

A CMOS Direct Conversion Transmitter With Integrated In-Band Harmonic Suppression for IEEE 802.22 Cognitive Radio Applications, Jongsik Kim, Seungsoo Kim, Jaewook Shin, Youngcho Kim, Junki Min*, Kihong Kim* and Hyunchol Shin, Kwangwoon University, Seoul, Korea, *Samsung Electro-Mechanics co., Suwon, Korea

A CMOS direct conversion transmitter for IEEE 802.22 cognitive radio applications is presented. In-band harmonic distortions are effectively suppressed across the full TV band by exploiting single-conversion dual-path architecture with integrated harmonic rejecting mixers and RF tunable filters. A fractional-N synthesizer with a single LC VCO and a wideband muti-modulus (2/3/4/6/8/12/16/24) divider block provide multiphase LO signals.  Implemented in 0.18 um CMOS, the transmitter delivers 0-dBm with in-band distortions less than -42 dBc across 54 - 862 MHz band without off-chip filters. Image and LO leakage components are also suppressed below -45 dBc and -36 dBc, respectively, through calibration circuitry. Measured P1dB and OIP3 are +9 dBm and +20 dBm, respectively.

11:15

19-6

A 5-GHz Wireless LAN Transmitter with Integrated Tunable High-Q RF Filter, Robert Wiser, Masoud Zargari, David Su and Bruce Wooley, Stanford University, Stanford, CA

A tunable high-Q RF filter has been demonstrated in an 802.11a sliding-IF transmitter implemented in standard CMOS. Two independent stagger-tuned Q-enhanced resonators form a filter centered at 5.145-GHz with 200-MHz bandwidth and 0.8-dB ripple. The transmitter provides spectral mask and EVM-compliant output power of –8.26 dBm for a 54-Mb/s signal.

8:30

20-1

A 6.5 Gb/s Backplane Transmitter with 6-tap FIR Equalizer and Variable Tap Spacing, Mike Bichan and Anthony Chan Carusone, University of Toronto, Toronto, Canada

This paper presents a 6.5 Gb/s transmitter for use in backplane links. This transmitter incorporates a finite impulse response filter with programmable tap spacing in the output driver to compensate for intersymbol interference.  Using jitter-minimizing tap weights computed using a behavioral model of the transmitter, it is shown that at 6.5 Gb/s peak-to-peak data-dependent jitter is reduced by over 50% by using a tap spacing of 0.53 unit intervals (UI) instead of the usual 1 UI.

8:55

20-2

Phase-Locking in Wireline Systems: Present and Future (INVITED), Behzad Razavi, University of California, Los Angeles, CA

This paper describes the challenges in the design of phase-locked loops and clock and data recovery circuits as speeds approach 80-100 Gb/s. Skew and jitter issues are presented and the effect of reference phase noise, charge pump noise, reference spurs, and loop filter leakage is quantified. The phase noise performance of cascaded loops is analyzed and two new architectures are proposed.

9:45

20-3

A 20Gb/s SerDes Transmitter with Adjustable Source Impedance and 4-tap Feed-Forward Equalization in 65nm Bulk CMOS, Rick Philpott, James Humble, Robert Kertis, Karl Fritz, Barry Gilbert and Erik Daniel, Mayo Clinic, Rochester, NY

Design and test results of a 20Gb/s Source-Series Terminated SerDes transmitter are presented. The integrated circuit, fabricated in 65nm bulk CMOS, transmits pre-emphasized data using a 4-tap feed-forward equalizer.  Output impedance is adjustable from 45 to 55 ohms. Measured power consumption is 167mW at 1.1V.

10:25

20-4

Wideband mmWave CML Static Divider in 65nm SOI CMOS Technology (INVITED), Daeik Kim, Choongyeun Cho, Jonghae Kim*, and Jean-Olivier Plouchart**, IBM Semiconductor R&D Center, *Qualcomm, San Diego, CA, **IBM T.J. Watson Research Center, Yorktown Heights, NY

A wideband millimeter-wave CML static divider fabricated in 65nm SOI CMOS is presented. Divider circuit analysis, sensitivity curve, simulations, and measurements are explored with input-locking hysteresis and DC bias tuning to extend the divider operation range. The divider exhibits wideband performance to overcome process variability in sub-100nm CMOS processes.

10:50

20-5

A 32/16 Gb/s 4/2-PAM Transmitter with PWM Pre-Emphasis and 1.2 Vpp per side Output Swing in 0.13-µm CMOS, Horace Cheng and Anthony Chan Carusone, University of Toronto, Toronto, Canada

A dual-mode 4/2-PAM transmitter is described that extends pulse-width modulated pre-emphasis to data rates of 16 Gb/s and 32 Gb/s in 2-PAM and 4-PAM modes respectively. Implemented in a 0.13-µm CMOS process to accommodate the wide output swing of 1.2 Vpp per side, the transmitter compensates for 30 dB and 9 dB of loss at one-half the symbol rate in 2-PAM and 4-PAM modes respectively.

11:15

20-6

A 5-Gb/s/pin Transceiver for DDR Memory Interface with a Crosstalk Suppression Scheme, Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park*, Young-Hyun Jun* and Kinam Kim*, KAIST, Daejeon, Rep. of Korea, *Samsung Electronics, Gyeonggi-Do, Rep. of Korea

A 5-Gbps/pin DDR memory transceiver is implemented with a crosstalk suppression scheme using 0.18um CMOS process. The proposed transceiver implements a staggered memory bus and a glitch canceller to suppress crosstalk. The eye-width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively.

11:40

20-7

EMI Resisting Smart-power Integrated LIN Driver with Reduced Slope Pumping, Jean-Michel Redouté and Michiel Steyaert, Katholieke Universiteit Leuven, Heverlee, Belgium

This paper presents a Local Interconnect Network (LIN) smart-power driver exhibiting a high immunity against electromagnetic interferences (EMI).  Improving previous designed architectures, this circuit is power friendly and less susceptible to slope pumping. Measurements show that this LIN driver withstands the 5W DPI (Direct Power Injection) measurement.

8:30

21-1

Stacking Technology Based on 8-inch Wafers using Direct Connection between TSV and Micro-bump, Nobuaki Miyakawa, Eiri Hashimoto, Takanore Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, and Shinjiro Toyoda, Honda Research Institute Japan Co., Ltd.

We have developed a unique TSV structure and evaluated the connectivity between TSV and micro-bump. The connection resistances are less than 0.7 ohm and the capacitance of TSV is less than 3pF, respectively. The electrical connection between each wafer was almost 100% and the functional yield reached more than 60%.

9:45

21-2

Clock Distribution Networks for 3-D Integrated Circuits, Vasilis Pavlidis, Ioannis Savidis and Eby Friedman, University of Rochester, Rochester, NY

Three-dimensional (3-D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. A comparison of three 3-D clock distribution network topologies and experimental results of a 3-D test circuit manufactured by the MIT Lincoln Laboratories are presented. Clock skew and power dissipation measurements are also provided.

10:25

21-3

Inter-Die Signaling in Three Dimensional Integrated Circuits, Christopher Mineo, Ravi Jenkal, Samson Melamed and W. Rhett Davis, North Carolina State University, Raleigh, NC

We discuss a 3D NoC fabricated in a 0.18um 3D process.  It is the first to demonstrate successful inter-tier signaling in a complex 3D design.  Simulations show that if using a 3D process, 3D mesh interconnection networks can share routing resources while consuming just 2 mW of power per transaction.

10:50

21-4

Variability in 3-D Integrated Circuits, Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra Jackson and Rajit Manohar, Cornell University, Ithaca, NY

In recent years, there has been some debate regarding applicability of 3-D technology to general circuits, especially due to thermal issues. We examine process variations on the same layer, across layers, and cross-chip variations. We show how performance of each layer of 3-D chip varies with temperature, and demonstrate the effect of heat pipes on circuit performance.

8:55

21-5

3D Heterogeneous Integrated Systems: Liquid Cooling, Power Delivery, and Implementation (INVITED), Muhannad Bakir, Calvin King, Deepak Sekar, Hiren Thacker, Bing Dang, Gang Huang, Azad Naeemi and James Meindl, Georgia Institute of Technology, Atlanta, GA

This paper describes a novel 3D integration technology that enables the integration of electrical, optical, and microfluidic interconnects in a 3D die stack. These interconnects are integrated in a 3D stack both as through-silicon vias (TSVs) and as input/output (I/O) interconnects. Design trade-offs (TSV density, power supply noise, thermal resistance, and pump size), fabrication, and assembly are reported.

11:15

21-6

SiP for GSM/EDGE in CMOS Technology, Giuseppe Li Puma, Ernst Kristan, Paolo De Nicola*, Cyril Vannier**, Braam Greyling*** and Salvatore Piccolella****, Infineon Technologies, Duisburg,Germany, *Sophia-Antipolis, France, **Xi'an, China, ***Villach, Austria, ****Padova, Italy

The development in the field of RF and baseband (BB) integration in nanoscale CMOS technology for cellular systems over the last recent years has shown significant progress [1], [3], [4] The successful integration of the RF transceiver with digital baseband processor enables mobile phone manufacturer to build ultra-low cost phones for GSM/GPRS in CMOS technology [2]. This trend towards continuous system integration for mobile phones with an advanced feature set providing high data rate communication, multimedia and camera capabilities [4]. The support of various features requires a system solution including the power-management unit (PMU) with highly efficient DC-DC converters to reduce the overall power consumption. However, this imposes a major challenge for the integration of the RF due to crosstalk and thermal heating effects caused by the PMU and BB part.

11:40

21-7

Heterogeneous Multicore SoC for Secure Multimedia Applications, Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka*, Yoshihiro Saito*, Kazutami Arimoto and Toru Shimizu, Renesas Technology Corp., Itami, Japan, *Renesas Solutions Corp., Osaka, Japan

A heterogeneous multicore SoC has been developed for HD multimedia applications that require secure DRM. To achieve secure data control, hardware memory management and software system virtualization are adopted. A highly tamper-resistant system is provided on our SiP, through DDR memories and Flash ROM that contain confidential information in one package.

12:05

21-8

A 159.2mW SoC Implementation of T-DMB Receiver including Stacked Memories, Joohyun Lee, Sungdo Kim, Jinkyu Kim, Duckhwan Kim, Youngsu Kwon, Minseok Choi, Kihyuk Park, Bontae Koo, Nakwoong Eum and Hyuckjae Lee*, ETRI, Korea, *Information and Communication University, Korea

This paper describes a system on chip (SoC) implementation of terrestrial digital multimedia broadcasting (T-DMB) receiver which integrates RF tuner, analog to digital converter (ADC), baseband processor, and multimedia processor in single silicon wafer. The pseudo-SRAM (PSRAM) and SDRAM are doubly stacked with method of silicon in package (SIP). A low-IF RF tuner and a 10bits pipelined ADC is used in this work as IP cores. Baseband processor contains Eureka-147 digital audio broadcasting (DAB) modem, MPEG1-Layer2 decoder, and outer decoder for T-DMB. Multimedia processor is consists of 32bit embedded micro processor, 24bit fixed-point DSP, and H.264/AVC hardware core. The T-DMB SoC was fabricated by using 0.13um 1poly 8metal (1P8M) CMOS process and it gives successful performance of 159.2mW total power dissipation including PSRAM and SDRAM at supply voltages of 1.2V, 2.5V for core and I/O respectively.

1:35

22-1

Modeling, Measurement and Mitigation of Crosstalk Noise Coupling in 3D-ICs, Liuchun Cai and Ramesh Harjani, University of Minnesota, Minneapolis, MN

Measurement and simulation results show that the crosstalk between the transmitter and receiver reduces by about 75dB up to 10GHz by using a Faraday cage in combination with tier to tier isolation in 3D ICs. There is good agreement between measurement, 3D electromagnetic simulation and lumped circuit simulation.

2:00

22-2

A Method Using Circuit/Substrate Macro Modeling to Analyze Substrate Noise in a 3.2-GHz 350M-transistor Microprocessor, Mikiki Sode, Mikihiro Kajita*, Naoya Nakayama and Satoshi Nakamoto, NEC Electronics Corporation, *NEC Corporation, Kanagawa, Japan

We have developed a fast substrate noise analysis method for Microprocessor class digital circuit at practical CPU time and accuracy. Domain-based macro modeling and recursive partition method by using current density variation is proposed. Experimental result shows practical CPU time is obtained while retaining good accuracy.

2:25

22-3

Characterization of Random Decision Errors in Clocked Comparators, Brian Leibowitz, Jaeha Kim, Jihong Ren and Christopher Madden, Rambus Inc., Los Altos, CA

Random noise in clocked comparators can lead to decision errors.  This paper describes a method to simulate random noise in comparators using linear periodically time-varying simulation techniques that have been used primarily for RF circuits. Simulated and measured random noise for two wireline receivers are compared to validate the method.

2:50

22-4

Noise Tolerant Oscillator Design Using Perturbation Projection Vector Analysis, Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Hanumolu, Un-Ku Moon and Kartikeya Mayaram, Oregon State University, Corvallis, OR

The impact of an oscillator's intrinsic and extrinsic noise sources on its noise performance is evaluated using the perturbation projection vector (PPV) analysis. The projection of a perturbation into the phase deviation for white and flicker noise, as well as for deterministic perturbations is explained qualitatively. The PPV analysis is then applied to two ring-type voltage controlled oscillators (VCO). Comparisons with measured results demonstrate the usefulness of the PPV analysis for design of noise tolerant oscillators.

3:15

22-5

Strong Injection Locking of Low-Q LC Oscillators, Mozhgan Mansuri, Frank O'Mahony, Ganesh Balamurugan, James Jaussi, Joseph Kennedy, Sudip Shekhar*, Randy Mooney and Bryan Casper, Intel Corporation, Hillsboro, OR, *University of Washington, Seattle, WA

This paper presents a new equation for injection-locked LC oscillators (ILOs) based on a series RL element in parallel with C. Unlike previous ILO equations based on a parallel RLC tank approximation, the proposed equation is valid for any tank Q and injection strength (K). The model reveals several important properties of low-Q and/or high-K ILOs such as asymmetry in the lock range, reduced phase shift, and higher bandwidth. Experimental results validate the model.

1:35

23-1

A Low Power 1.3GHz Dual-Path Current Mode Gm-C Filter, Manisha Gambhir, Vijay Dhanasekaran, Jose Silva-Martinez and Edgar Sanchez-Sinencio, Texas A&M University, College Station, TX

A class-AB, dual path building block for Gm-C filter that has high linearity and high PSRR is presented. A current-mode 4th order Butterworth filter designed using the proposed building block in 0.13um CMOS provides 54dB IM3 and 52dB SNR in 1.3GHz bandwidth while consuming only 24mW. It occupies 0.1sqmm.

2:00

23-2

A 1V Downconversion Filter Using Duty-cycle Controlled Bandwidth Tuning, Peter Kurahashi, Pavan Kumar Hanumolu and Un-Ku Moon, Oregon State University, Corvallis, OR

This paper describes a downconversion filter which uses variable delay clocks to simultaneously perform downconversion mixing and filter bandwidth tuning. This method of bandwidth tuning is highly linear and applicable to low supply voltages. The test chip fabricated in a 0.18um CMOS process achieves 19.2dBV IIP3 at 1V and has a bandwidth that is tunable over a +-50% range. The downconversion filter mixes and filters an 830MHz input to a nominal 300kHz bandwidth at DC.

2:25

23-3

A Reconfigurable FIR Filter Embedded in a 9b Successive Approximation ADC, Joshua Kang, David Lin, Li Li and Michael Flynn, University of Michigan, Ann Arbor, MI

A reconfigurable FIR filter is embedded into a 9b SAR ADC by modifying the input tracking switches of the capacitive DAC.  The filter-ADC combination can assist or eliminate the anti-aliasing or channel selection filtering stages in a digital radio receiver.  Three different filtering modes are implemented and tested.

2:50

23-4

Voltage References for Ultra-Low Supply Voltages (INVITED), Peter Kinget, Christos Vezyrtzis, Ed Chiang, B. Hung* and T.L. Li*, Columbia University, New York, NY, *United Microelectronics, Taiwan, ROC

The majority of integrated voltage references have, so far, been limited to a minimum supply voltage above 0.7-V often due to the voltage headroom required for the forward-biased operation of a PN-junction. This paper reviews design techniques for low voltage reference design and explores the feasibility of designing a voltage reference with a supply voltage below 0.7-V in a standard CMOS process. Two ultra-low-voltage solutions are explored in detail, a reference circuit based on CMOS compatible Schottky diodes and a MOS-only reference circuit.

3:15

23-5

Design of Bandgap Voltage Reference Circuit with all TFT Devices on Glass Substrate in a 3-um LTPS Process, Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Chung-Hung Kuo*, Chun-Huai Li*, Yao-Jen Hsieh* and Chun-Ting Liu*, National Chiao Tung University, Taiwan, ROC, *AU Optronics Corporation, Taiwan, ROC

A BGR designed with the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on glass substrate is proposed, which has been successfully verified in a 3-um LTPS process. The experimental results have shown that the measured TC of the new proposed bandgap voltage reference circuit is around 195 ppm/°C under the supply voltage of 10V.

3:40

23-6

Deep Submicron Effects on Data Converter Building Blocks (INVITED), William Evans and David Burnell, Cadence Design Systems, Columbia, MD

Physical effects in deep submicron processes affect reliability, performance, and functionality of common data converter circuit blocks.  NBTI (Negative Bias Temperature Instability), STI (Shallow Trench Isolation) stress, and NWELL proximity effects are reviewed and examples given of circuit and layout practices which can minimize the adverse effects on these blocks.

1:35

24-1

A Highly Linear SAW-less CMOS Receiver Using a Mixer with Embedded Tx Filtering for CDMA, Namsoo Kim, Lawrence E. Larson and Vladimir Aparin*, University of California, La Jolla, CA, *Qualcomm, San Diego, CA

An embedded filtering passive receiver mixer is used to overcome transmitter power leakage without the use of a SAW filter. The receiver IC exhibits more than +60dBm of Rx IIP2, 2.4dB Rx NF, and +77dB of Triple Beat (TB) with 45MHz transmit leakage at 900MHz Rx frequency while consuming only 18mA from a 2.1V supply.

2:00

24-2

High-power Digital Envelope Modulator for a Polar Transmitter in 65nm CMOS, Manel Collados, Paul T.M. van Zeijl* and Nenad Pavlovic, NXP Semiconductors Research, Eindhoven, The Netherlands, *Philips Research, Eindhoven, The Netherlands

An 8-bit envelope modulator as part of a digital polar transmitter for  Bluetooth and WLAN is demonstrated. The modulator performs digital-to-analog  conversion, up-mixing and power amplification. It delivers 16.7dBm OFDM  power with 2.7% EVM and a drain efficiency of 24%. The circuit uses 5nm thick-oxide devices and 2.5V supply.

2:25

24-3

A 2.4GHz, 20dBm Class-D PA with Single-Bit Digital Polar Modulation in 90nm CMOS, Jason T. Stauth and Seth R. Sanders, University of California, Berkeley, CA

A 90nm CMOS digital-polar transmitter with class-D PA achieves peak efficiency of 38.5% at 2.4GHz including driver power and filter insertion loss.  The system achieves rms EVM of 1.8-2.1% and average efficiency of 30% for pi/4DQPSK and 8DPSK modulation signals without predistortion.

2:50

24-4

Linearity and Efficiency Enhancement Strategies for 4G Wireless Power Amplifier Designs (INVITED), Larry Larson, Donald Kimball and Peter Asbeck, University of California, San Diego, CA

Next generation wireless transmitters will rely on highly integrated silicon-based solutions to realize the cost and performance goals of the 4G market. This will require increased use of digital compensation techniques and innovative circuit approaches to maximize power and efficiency and minimize linearity degradation. This paper summarizes the circuit and system strategies being developed to meet these aggressive performance goals.

3:50

24-5

An Analog Enhanced All Digtial RF Fractional-N PLL With Self-Calibrated Capability, Ping-Ying Wang, Jing-Hong Zhan, Hsiang-Hui Chang and Bing-Yu Hsieh, Media Tek Inc., Taiwan, ROC

A 3.2GHz to 4.0GHz analog enhanced all digital fractional-N PLL with self-calibrated capability is proposed. An analog feed-forward circuits replace the time-to-digital converter used in conventional all digital PLL (ADPLLs) to provide a linear phase modulation path which is insensitive to quantization error and non-linearity of digital controlled oscillator (DCO). Its advantages include 1) Eliminating fractional spurs and noise induced by quantization error and the latency induced by the digital circuits in ADPLLs 2) Relaxing both digital controlled oscillator (DCO) and analog feed-forward circuit design requirements. 3) Calibrating analog feed-forward design parameter by using the digital loop filter.  4) Reducing loop filter area by using digital loop filter. The fractional spurs are 9 to 30dB lower than the latest reported ADPLLs. At 3.6GHz under fractional-N mode operation, the fractional spur is under -75 dBc, the phase noise is -115.6dBc/Hz @400KHz, -134.9dBc/Hz @3MHz. The performance satisfies GSM/GPRS/EDGE system requirements.

4:15

24-6

A Delta-Sigma Fractional-N Synthesizer with Customized Noise Shaping for WCDMA/HSDPA Applications, Xueyi Yu, Yuanfeng Sun, Woogeun Rhee, Zhihua Wang, Hyung Ki Ahn* and Byeong-Ha Park*, Tsinghua University, Beijing, China, *Samsung Electronics Co., Ltd., Yongin-City, Korea

This paper describes a quantization noise reduction method in delta-sigma fractional-N synthesizer design based on a semidigital approach. By employing a phase shifting technique, a low power hybrid finite impulse response (FIR) filtering is realized which is suitable for RF applications. A prototype fractional-N synthesizer is implemented in 180nm CMOS for WCDMA/HSDPA applications. Experimental results show that the proposed method can effectively suppress out-of-band phase noise to meet the phase noise mask requirements in various RF applications.