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2010 VLSI Circuits Short Course Program Circuit Design for Technology Challenges Tuesday, June 15, Honolulu I Organizers/Chairs: Azeez Bhavnagarwala, IBM TJ Watson Research Koichi Nose, Renesas Corp. 8:30 a.m. Introduction A. Bhavnagarwala, IBM TJ Watson Research 8:45 a.m. CMOS Technology Trends G. Shahidi, IBM TJ Watson Research 9:45 a.m. CMOS Logic and Embedded Memory Design K. Zhang, Intel 10:45 a.m. Break 11:00 a.m. Design Methodology and Tools in an Evolving CMOS Technology C. Bittlestone, Texas Instruments 12:00 p.m. Lunch 1:00 p.m. Analog/Mixed Signal Design in Digital CMOS D. Fishette, AMD 2:00 p.m. Chip-Package-Co-Design A. Nakamura, Renesas 3:00 p.m. Break 3:15 p.m. Memory Design - Low Power DRAM Circuits and Interface Design - Y. Takia, Elpida Memory Design - Distrubance and Interference Issues in NAND Flash Design - Y.T. Lee, Samsung 5:15 p.m. Conclusion M. Ito, Renesas Technology Corp. Frequency Synthesis and Clock Generation Tuesday, June 15, Honolulu II Organizers/Chairs: Andreia Catheliln, STMicroelectronics Shin'ichiro Mutoh, NTT 8:30 a.m. Introduction A. Cathelin, STMicroelectronics 8:45 a.m. Basics of Jitter and PHase Noise A. Abidi, UCLA 9:45 a.m. Modeling/Simulation of Large Signal Phenomena in PLL R. Poore, Agilent EEs of EDA 10:45 a.m. Break 11:00 a.m. Architecture Trends and Requirements for Wireless RF PLLs C-M Hung, Texas Instruments 12:00 p.m. Lunch 1:00 p.m. Low Frequency Synthesis Using BAW/IC B. Otis, University of Washington 2:00 p.m. Clocking Techniques for High-Speed Wireline J-Y Sim, POSTECH 3:00 p.m. Break 3:15 p.m. Mm-Wave PLL Design T. Mitomo, Toshiba Corp. 4:15 p.m. Round Table (all speakers) 5:00 p.m. Conclusion *Breakfast and Coffee are provided.